tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 356

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
16 Microprocessor Interface Functional Description
16.4 MPU Block Diagram
16.5 Super Mapper Register Address Mapping
Each of the Super Mapper’s major functional blocks is selected with an address mapping of the highest order nib-
ble, device pins ADDR[19:16], and allocated a 16-bit address range, pins ADDR[15:0], as defined in
Table 521. Super Mapper Register Address Mapping
16.6 Performance Monitoring (PM) Counters Operation
PM counters are error counters or other statistics counters. In general, two internal registers are needed to imple-
ment a PM counter: a running count register (1), maintained by the core logic, which is incremented by 1, every
time an error (or statistics event) happens. At a defined interval, one second for example, the content of the running
counter is transferred to a holding register (2), while the running count register is reset to 0 and starts to count
anew. The count holding register holds the data that microprocessor actually reads.
356
ADDR[19:16]
0000
0001
0010
0011
0100
0101
0110
0111
1000
ADDR[19:0]
DATA[15:0]
APS_INTN
MPMODE
PAR[1:0]
MPCLK
ADSN
RWN
CSN
DSN
INTN
DTN
Figure 18. Microprocessor Interface
Block ID
0
1
2
3
4
5
6
7
8
Block Name
(continued)
SPEMPR
FRAMER
VTMPR
TMUX
TOP
TPG
M13
DJA
XC
INTERNAL
INTERNAL
INTERNAL
ADDRESS
CONTROL
DATA
Agere Systems Inc.
ADDR
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Table
May 2001
521.
5-9039(F)r.2