tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 573

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
23 Digital Jitter Attenuation Controller Functional Description
23.4.1 PLL Bandwidth and Damping Factor Control
Two programmable terms are used to set the second-order loop damping factor and natural frequency. These
terms are the gain threshold, set by registers DJA_E1GAIN[26:0]
(Table
(Table
values in decimal and hexadecimal terms to achieve these parameter values are listed in
Table 622. PLL Bandwidth Control Parameters
23.4.2 PLL Order Control
Under normal conditions the DJA blocks operate in the second-order PLL mode. This operation attempts to keep
the elastic store at the center of its range. However, following a VT pointer adjustment, it may be desirable to have
the DJA blocks operate in the first-order mode. This is because the maximum timing interval error (MTIE)
specification (GR-253, requirement R5-132) doesn’t allow for any peaking. The second-order loop has a certain
amount of peaking in its transient response that the first-order loop eliminates. The amount of time that the block
operates in the first-order mode is programmable between 0 ms and 1 second.
This operation is accomplished by loading a count value into registers DJA_E1PTRADJCNT[20:0] or
DJA_DS1PTRADJCNT[20:0]
VT pointer adjustment takes place. The counter decrements every XCLK/16 or XCLK/32 clock period until it
reaches 0. While the count is nonzero, the block operates in the first-order mode. By default, the
DJA_E1PTRADJCNT or DJA_DS1PTRADJCNT value is 0, so the block never switches into the first-order mode
until programmed to do so. Some example time period durations and the corresponding decimal and hexadecimal
DJA_E1PTRADJCNT and DJA_DS1PTRADJCNT values are listed in
Table 623. First-Order Mode Duration Control
23.4.3 DS1/E1 Clock Edge Control
The active edges on both the input and the output DS1/E1 signals are selectable via registers in
DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W) on page
DJA_TXEDGE[28:1]
edge). DJA_RXEDGE[28:1] controls the edge that the data transitions on when retimed into the DJA (1 = rising
edge).
Agere Systems Inc.
0.75 0.325
0.5
1.0
1.5 0.175 21,827
2.0 0.125 40,743
d
473), and scale value, set by registers DJA_E1SCALE[15:0]
475). Some values of damping factor (d) and natural frequency ( n) are listed below. The GAIN and SCALE
0.45
0.25
Duration
n
250 ms
500 ms
750 ms
1 s
—
10,186
2,829
5,876
dec
E1_SCALE
(Table
0x27CA
0x16F4
0x9F27
0xB0D
0x5543
hex
479) controls the edge that the data transitions on when leaving the DJA (1 = rising
(Table
1,024,000
1,536,000
2,048,000
512,000
104,000,000
15,348,087
25,938,267
52,935,238
dec
476,
8,005,638
dec
Table
E1_GAIN
E1 Mode
477). The value in this register is loaded into a counter whenever a
0x18BC95B
0x327BA46
0x632EA00
0x7A2806
0xEA3177
hex
0x1F4000
0x177000
0xFA000
0xC800
hex
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table
16,455
30,716
2,133
4,430
7,679
(Table
dec
DS1_SCALE
Table
472) and DJA_DS1GAIN[26:0]
474) and DJA_DS1SCALE[15:0]
0x1DFF
0x77FC
0x114E
623.
0x4047
1,158,000
1,544,000
TMXF28155/51 Super Mapper
0x855
386,000
77,200
hex
dec
14,741,431
30,084,553
58,965,723
DS1 Mode
4,549,825
8,722,740
Table
(continued)
dec
DS1_GAIN
622.
Table 479,
334.
0x11AB70
0x178F40
0x12D90
0x96C8
0x1CB0DC9
0x383BEDB
hex
0x456CC1
0xE0EFB7
0x851934
hex
573