tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 416

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
18.14.10 REI-P Detect
Bits 7 through 4 of the G1 byte are allocated for use as a path remote error indication function (REI-P).
Table 544. STS-1 P-REI Interpretation
The SPE mapper provides a counter to accumulate G1-REI errored bit count in SPE_G1ECNT[15:0]
page
processor bit SMPR_SAT_ROLLOVER
val.
18.14.11 Signal Degrade BER Algorithm
A signal degrade state bit is SPE_SDB3
bit SPE_SDB3D
algorithm operates on B3 errors.
Declaring the signal degrade state requires the definition of two measurement windows. A monitoring block con-
sisting of a number of frames, Ns (SPE_SDNSSET[18:0]
consisting of a number of monitoring blocks, B (SPE_SDBSET[11:0]
the number of bit errors equals or exceeds a threshold, L (SPE_SDLSET[3:0]
declared when a number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SDMSET[7:0]
(Table
Clearing the signal degrade state requires the definition of two measurement windows. A monitoring block consist-
ing of a number of frames, Ns (SPE_SDNSCLEAR[18:0]
number of monitoring blocks, B (SPE_SDBCLEAR[11:0]
ber of bit errors is less than a threshold, L (SPE_SDLCLEAR[3:0]
number of good monitoring blocks equals or exceeds the threshold, M (SPE_SDMCLEAR[7:0]
measurement interval.
The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the
signal degrade state is declared.
The signal degrade state may be forced to the declared state with bit SPE_SDSET
forced to the cleared state with bit SPE_SDCLEAR
rithm into the failed state or normal state, respectively.
The above algorithm can detect bit error rates from 1 x 10
416
For STS-1 signals, bits 7 through 4 of the G1 byte are allocated for REI-P which conveys the error count detected
by the PTE (using the path BIP-8 code B3) back to its peer PTE as follows.
147) from G1[7:4]. This counter will hold at its maximum value or roll over (depending on the value of micro-
158)), for the measurement interval.
(Table 146 on page134
G1[7:4] Code
1001—1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
(Table 67 on page
(Table 148 on page
) and the interrupt mask bit is SPE_SDB3M
(Table
(continued)
(Table
(Table 158 on page
(Table
–3
145). The controls are provided to force the BER algo-
68)) and update upon the performance monitoring inter-
137) with a change of state indication reported in delta
to 1 x 10
158)). A block is determined good when the num-
158)), and a measurement interval consisting of a
(Table
(Table
–9
.
158)). Signal degrade is cleared when a
Code Interpretation
158)). A block is determined bad when
0 (no errors)
0 (no errors)
146)), and a measurement interval
(Table
1
2
3
4
5
6
7
8
(Table 145 on page134
(Table
158)). Signal degrade is
147). This bit error rate
(Table
Agere Systems Inc.
(Table 160 on
158)), for the
May 2001
) and