tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 592

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
26 Applications
On the receive side, pointer interpretation is performed detecting LOP, AIS, NDF, NORM, INC, and DEC. A DS3
loopback mode allows demapping and remapping of a DS3 signal. It is particularly useful in cases where a DS3
signal mapped as an AU-3/STS-1 signal is needed to be remapped as a TU-3 signal or vice versa. B3ZS encoding/
decoding is included.
The same path overhead monitoring functions as described above are implemented in this block.
This block also connects to the path overhead access channel (POAC) to insert/drop the path overhead bytes J1,
C2, F2, H4, F3, K3, and N1 into the STS-1 SPE or VC-3.
The SPE mapper
function.
The SPE mapper
26.8 VT/VC Mapper
The VT/VC mapper maps any valid combination of DS1 and E1 signals into a stream at a rate of 51.84 Mbits/s
(STS-1 or AU-3). The mapping methods (VT1.5, VT2, and VT group in ANSI nomenclature; TU-11, TU-12, and
TUG-2 in ITU nomenclature) are analogous. The VT/VC mapper supports the following mappings:
ADM and unidirectional path switch ring (UPSR) applications are supported via tributary loopback, tributary pointer
processing, and low-order path overhead access channel.
The VT/VC mapper
automatic downstream AIS generation, and five J2 trace identifier modes.
The VT/VC mapper
417-1-1.
26.8.1 Receive Direction
In the receive direction, the VT mapper terminates the data stream it receives from the SPE mapper. It demulti-
plexes the AU-3/TUG-3 into the VTs/TUs and checks the H4 multiframe alignment. Pointer interpreters for up to
28 VTs/TUs detect LOP, AIS, NDF, NORM, INC, and DEC on each channel.
The low-order path termination includes V5 byte termination, J2 path trace, Z6/N2 tandem connection, Z7/K4
enhanced RDI and low-order APS monitor, and the payload termination for asynchronous, byte- or bit-synchronous
signals. The V5 byte termination performs BIP-2 check (bit- or block-mode), REI count, RFI and RDI detection, sig-
nal label monitor, and automatic AIS insertion (which can be inhibited). The J2 monitor supports four different
modes as follows:
In byte-synchronous modes, the receive demapper generates a frame sync to indicate the DS1 frame bit or the
MSB of the E1 time slot 0. Additionally, it provides the framer access to the received signaling bits. Output of the VT
mapper is a DS1/J1/E1 signal with a gapped clock. It can be overwritten with AIS automatically or upon micropro-
cessor request.
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28 asynchronous, byte- or bit-synchronous DS1 signals are mapped into seven VT groups or TUG-2s.
28 asynchronous, byte- or bit-synchronous J1 signals are mapped into seven VT groups or TUG-2s.
21 asynchronous, byte- or bit-synchronous E1 signals are mapped into seven VT groups or TUG-2s.
Maps T1 into VT1.5/TU-11/TU-12, J1 into VT1.5/TU-11/TU-12, and E1 into VT2/TU-12.
Cyclic check
SONET framing mode
SDH framing mode
Single byte check.
supports unidirectional path switch ring (UPSR) applications as well as N1 tandem connection
complies with GR-253-CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, and ETS 300 417-1-1.
supports automatic generation or microprocessor overwrite 1-bit RDI, enhanced RDI, 1-bit RFI,
complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, and ETS 300
(continued)
Preliminary Data Sheet
Agere Systems Inc.
May 2001