tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 441

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description
19.14.1 Input Selector (INSEL)
The INSEL logic block (in
detection. The following features will be implemented:
Transmit mapping modes are shown in
Table 558. Transmit VT/TU Mapping Selection per Channel, VT_TX_MAPTYPE[1—28][3:0]
Agere Systems Inc.
The incoming DS1/E1 signal will be retimed immediately using the selected DS1/E1 clock edge
(VT_TX_CLKEDGE[1—28]
DS1/E1 CLOCK is used to retime the signal; otherwise, the falling edge is used.
The incoming DS1/E1 signals will be checked for a digital loss of clock (LOC) condition and reported with bit
VT_TX_LOC[1—28]
sor via bit VT_TX_LOC_D[1—28]
VT_TX_LOC_D = 1 will generate an interrupt.
If LOC is detected (VT_TX_LOC[1—28] = 1), DS1/E1 AIS will be inserted in the appropriate transmit path VT.
DS1/E1 AIS consists of a valid VT/TU pointer, valid VT/TU overhead, and an all ones payload.
In the byte-synchronous mode, the incoming DS1/E1 frame sync is monitored for the loss of frame sync condi-
tion (LOFS) and reported in bit VT_LOFS[1—28]
following three consecutive valid frame sync pulses (375 µs). Loss of frame sync (VT_LOFS[1—28] = 1) is
declared following six consecutive frame sync mismatches (750 µs). Any change in state of VT_LOFS[1—28] will
be reported in bit VT_LOFS_D[1—28]
VT_LOFS_D[1—28] = 1 will generate an interrupt.
If LOFS is detected (VT_LOFS[1—28] = 1), AIS-V is inserted in the appropriate VT location. AIS-V consists of
writing an all ones pattern into the entire VT, including V1~4.
The incoming DS1/E1 signal will be checked for the AIS condition and reported in bit VT_TX_AIS[1—28]
(Table
Unless the VT_TX_AIS_M[1—28]
rupt.
If the incoming data is DS1, AIS will be declared if there are less than nine zeros out of 8192 clock periods. If the
incoming data is E1, AIS will be declared if there are less than three zeros in each of two consecutive 512-bit
periods and cleared when each of two consecutive 512-bit periods contain more than two zeros.
VT_TX_MAPTYPE[1—28][3:0] (See
0
0
0
0
0
0
1
1
1
179). Any change in state of VT_TX_AIS[1—28] is reported in bit VT_TX_AIS_D[1—28] (
0
0
0
0
1
1
0
0
0
0110—0111
1011—1111
(Table
Figure 39 on page429
179). Any change in state of VT_TX_LOC[1—28] will be reported to the microproces-
(Table
0
0
1
1
0
0
0
0
1
(Table
(Table
198)). If VT_TX_CLKEDGE[1—28] = 1, the rising edge of the incoming
Table 558
Table
(Table
171). Unless the VT_TX_LOC_M[1—28]
175) mask bit is set, VT_TX_AIS_D[1—28] = 1 will generate an inter-
0
1
0
1
0
1
0
1
0
198.)
171). Unless the VT_LOFS_M[1—28]
) will perform loss of clock (LOC), AIS, and loss of frame sync
below.
(Table
Asynchronous VT1.5/TU-11 (DS1 input).
Asynchronous VT2/TU-12 (E1 input).
Byte synchronous VT1.5/TU-11 (DS1 input).
Byte synchronous VT2/TU-12 (E1 input).
Bit synchronous VT1.5/TU-11 (DS1 input).
Bit synchronous VT2/TU-12 (E1 input).
Undefined, generates VT1.5/TU-11 UNEQ-V.
Asynchronous VT2/TU-12 (DS1 input).
Byte synchronous VT2/TU-12 (DS1 input).
Bit synchronous VT2/TU-12 (DS1 input).
Undefined, generates VT2/TU-12 UNEQ-V.
(continued)
179). In frame sync, (VT_LOFS[1—28] = 0) is declared
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
TMXF28155/51 Super Mapper
Description
(Table
(Table
175) mask bit is set,
175) mask bit is set,
Table
171).
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