tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 393

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
17 TMUX Functional Description
Table 535
The TMUX allows a default value (all zeros if microprocessor interface block SMPR_OH_DEFLT = 0
page
nals are active-high.
Table 535. TTOAC Control Bits in Full Access Mode
An event indication must be provided to indicate parity errors for the TOAC channel. Odd or even parity is checked
depending on TMUX_TTOAC_OEPMON
parity error is reported in status register bit TMUX_TTOAC_PE
maskable with TMUX_TTOAC_PM
17.6.17 Sync Status Byte (S1) Insert
When TMUX_THSS1INS = 1
inserted into the S1 byte of the outgoing signal; otherwise, the associated TOAC value is inserted when
TMUX_TTOAC_S1 = 1
then the value inserted depends on the value of the microprocessor interface block SMPR_OH_DEFLT
on page68
inserted.
17.6.18 REI-L: M1 Insert
For STS-3/STM-1 modes, the M1 byte is allocated for use as a line remote error indication (REI). For STS-1, bits 0
to 3 of the M0 byte are used. The M0 or M1 bytes convey the count of interleaved bit blocks that have been
detected in error by the line BIP-8 (B2) detector on the received signal.
This function can be inhibited by asserting TMUX_THSLREIINH
byte can be inserted under user control. When TMUX_TLREIINS
sponding M0 or M1 byte will indicate one error each time the microprocessor interface block SMPR_BER_INSRT
(Table
The TMUX provides a protection switch MUX for REI-L insertion, controlled by TMUX_TLREIRDISEL
If TMUX_TLREIRDISEL = 1, then the REI-L value for insertion is taken from the value on the protection board
rather than from the receive side of the same TMUX.
17.6.19 APS Value and K2 Insert Control Parameters
When TMUX_THSAPSINS = 1
from TMUX_TAPSINS[12:0]
depending on the value of microprocessor interface block SMPR_OH_DEFLT
Agere Systems Inc.
All remaining bytes
Overhead Bytes
in
68), and all ones if SMPR_OH_DEFLT = 1) to be inserted on the corresponding TOAC value. All control sig-
D4—D12
D1—D3
65) bit is asserted.
Table 534
E1
S1
E2
F1
summarizes the insertion options for the specified overhead bytes for TOAC in full TOH access mode.
) bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are
TMUX_TTOAC_D4TO12
TMUX_TTOAC_D1TO3
(Table 117 on pag
TMUX_TTOAC_AVAIL
TMUX_TTOAC_E1
TMUX_TTOAC_S1
TMUX_TTOAC_E2
TMUX_TTOAC_F1
(Table
(Table 107 on page
Register Control Bits
(Table
(Table 84 on page87
113). When TMUX_THSAPSINS = 0, either all 0s or all ones will be written,
107), the K1 byte and the five most significant bits of the K2 byte are written
(Table 117 on page
e113). If both TMUX_THSS1INS and TMUX_TTOAC_S1 are a logic 0,
(Table
(Table
(Table
(Table
(continued)
(Table
(Table
(Table
103), the value in TMUX_TS1INS[7:0]
117)
117)
117)
117)
117)
117)
117)
).
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
113); 0 selects odd parity and 1 selects even parity. A
(Table 80 on pag
(00000000 or 11111111)
(Table 107 on page103
(Table 115 on page112
SMPR_OH_DEFLT
0 (Default Value)
Value of the Register Control Bits
TMXF28155/51 Super Mapper
(Table
e78), and the interrupt is
67) bit.
(Table 112 on page
). A bit error in the M0/M1
) is asserted the corre-
TOAC Data
(Table 67 on
(Table
1
(Table 67
110) is
107).
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