tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 501

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
The signaling will be byte sync mapped based on the standards listed below.
21.15 Optional Transmit Signaling Features Provisioned for Each Link
21.15.1 Support of Automatic Maintenance of the Time-Slot 16 Remote Frame Alarm
For CEPT links, the time slot 16 remote frame alarm (Y bit) can be automatically maintained in the transmit path by
setting FRM_T_ATS16RFA in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W),
bit 14, to 1. In that case, the Y bit transmitted will reflect the TS16 multiframe alignment status in the receive path.
Bit 1 in the transmit signaling link register 0 will be ignored. If the receive path time slot 16 alignment for a particular
link is lost, then the corresponding Y bit in the transmit path will be set to 1.
21.15.2 Support of DS1 Robbed-Bit Stomping
The DS1 robbed-bit positions of voice time slots will be set to 0 in the payload when FRM_T_TXSTOMP in
FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 7 is set to 1. This feature is a programmable option
required for byte sync mapping.
21.15.3 Support of CEPT Time-Slot 16 Stomping
Stomping of time slot 16 for CEPT links can by accomplished by setting the source of signaling to be the host and
then programming the transmit signaling link registers 0—31 to all ones.
21.15.4 Support of Signaling Debounce
If programmed to do so, the signaling extracted from the receive line interface will be debounced. This implies that
a valid signaling code would have to be detected twice before it is updated in the transmit signaling link registers
0—31. This feature is enabled by setting FRM_T_SIGDEB in FRM_TSLR32, Transmit Signaling Link Register 32
(R/W), bit 5 to a 1.
21.15.5 Support of Japanese Handling Groups
If the signaling is transported by the VT mapper within four handling groups compliant to the Japanese standard,
TTC JT G.704, then FRM_T_HGEN in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 4, must be set
to 1. The signaling state mode will be assumed to be 2-state signaling, and the value programed into the GF bits of
the transmit signaling link registers 0—31 will be ignored.
By default, the transmit signaling processor will drive the Sp bit of each handling group on each link to 1.This bit
can be manually forced to 0 for all the handling groups within a link by setting FRM_T_MSP in FRM_TSLR32,
Transmit Signaling Link Register 32 (R/W), bit 11, to 1. The Sp bit can be automatically maintained by setting
FRM_T_ASPLB in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 12, to 1. In that case, the Sp bits
in the transmit path will reflect the corresponding handling group alignment in the receive path. For example, if HG2
on link 3 is the only HG out of alignment on that link, then the Sp bit transmitted to the VT mapper for HG2 will be
set to 0. The Sp bit for HG 1, 3, and 4 will be set to 1.
21.15.6 Support of Zero-Code Suppression
If the frame formatter is configured to perform zero-code suppression, then FRM_T_ZCSM in FRM_TSLR32,
Transmit Signaling Link Register 32 (R/W), bit 10, must be set to 1. Zero-code suppression in the frame formatter is
enabled by programming FRM_ZCSMD[2:0] in FRM_FFLR1, Frame Formatter Link Register 1 (R/W),
page
Agere Systems Inc.
ANSI T1.105 SONET Payload Mapping
Telcordia GF-253-CORE SONET Transport Systems
ITU Rec G.707 10/98 Network Node Interface for SDH
300, bits [10:8].
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
TMXF28155/51 Super Mapper
Table 378 on pag
Table 424 on
e272,
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