tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 205

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers
Table 223. M13_MASK5, Mask (R/W)
Table 224. M13_DS3_STATUS1, Status (RO)
Agere Systems Inc.
Address
Address
0x1000E 15:2
0x1000F 15:8
Bit
Bit
7
6
5
4
3
2
1
0
1
0
M13_DS3_IDLEPAT_DET The 4704 information bits in each M frame are checked for
M13_DS2DMX_LOC_SM Setting this mask bit high prevents the summary delta
M13_DS3_AISPAT_DET The 4704 information bits in each M frame are checked for
M13_RDL_FIFO_UFM
M13_DS3_CBZ_DET
M13_DS3_RAI_DET
M13_DS3_C1_DET
M13_RDL_IDLE
M13_DS3_OOF
M13_DS3_LOF
Name
Name
—
—
Reserved.
This bit is set if 15 consecutive ones are received on the
path maintenance data link. it is cleared when a flag byte is
received.
This bit is set if M13_DS3_OOF is high continuously for
28 frame periods (approximately 3 ms). Once set,
M13_DS3_LOF is not cleared until M13_DS3_OOF is con-
tinuously low for 28 frame periods.
The DS3 framer out-of-frame state bit. (See DS3 Framer
on
This bit is set if the first C bit of each DS3 frame is received
high for 8 consecutive frames. Once M13_DS3_C1_DET is
set, 3 consecutive frames with C1 = 0 must be received
before it is cleared.
If both X bits in 2 consecutive frames are received as 0, the
M13 sets this bit to 1. Once it is set, it is not cleared until
both X bits in 2 consecutive frames are received as 1.
the presence of the AIS (1010) pattern. A pattern detection
bit is set if fewer than 5 pattern errors are received in each
of 2 consecutive frames. Once a bit is set, it is not cleared
until at least 16 pattern errors are received in each of
2 consecutive frames.
the presence of the idle (1100) pattern. A pattern detection
bit is set if fewer than 5 pattern errors are received in each
of 2 consecutive frames. Once a bit is set, it is not cleared
until at least 16 pattern errors are received in each of
2 consecutive frames.
This bit is set if every C bit in 3 consecutive DS3 frames is
0. It is cleared if the three C bits in a single
M-subframe are all 1.
Reserved.
M13_DS2DMX_LOC_SD
block output interrupt (INT) to be active.
Setting this mask bit high prevents M13_RDL_FIFO_UFD
(Table
page
(continued)
218) from causing the block output INT to be active.
469) This bit is high while out-of-frame.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
Function
(Table
TMXF28155/51 Super Mapper
218) from causing the
Default
000000
000000
Default
Reset
Reset
0x00
00
1
1
1
0
1
0
0
0
0
0
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