tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 390

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
17.6.8 Path RDI (RDI-P) Insert
When TMUX_THSRDIPINS = 1
on page110
STS-1 signal carries its own G1 value. For STM-1 mode, only TMUX_TRDIPINS1[2:0] is written into the first
STS-1 location. When TMUX_THSRDIPINS = 0, hardware insert is enabled for RDI-P insertion. Each defect contri-
bution to the RDI-P outgoing code can be inhibited. There are two modes supported for path RDI insertion. One
mode conforms to the earlier one-bit version of the standard. The other mode, enhanced RDI-P mode, uses a 3-bit
RDI-P code and conforms to the current version of the standard. When TMUX_TEPRDI_MODE = 0
page
TMUX_TEPRDI_MODE = 1, the TMUX will send a 3-bit code conforming to the current enhanced path RDI encod-
ing. Note that for non-enhanced RDI-P mode, the relevant defects are AIS-P and LOP-P. For enhanced RDI-P
mode, the relevant defects are AIS-P, LOP-P, PLM-P, and UNEQ-P.
When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must
last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
Table 532
Table 532. RDI-P Defects for Enhanced RDI-P Mode
The TMUX provides a protection switch MUX for RDI-P insertion. The MUX is controlled by TMUX_TPREIRDISEL
(Table 107 on page
the protection board rather than from the receive side of the same TMUX.
17.6.9 REI-P: G1(7:4) Insert
Four bits of the G1 byte G1(7:4) are allocated for use as path remote error indication (REI). For STS-1 signals and
for STM-1 signals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been
detected in error by the BIP-8 (B3) detector on the received signal.
The automatic insertion of path REI can be inhibited on an STS-1 basis by programming the corresponding register
bits TMUX_TPREIINS[1:3]
bit(s) TMUX_TPREIINS[1:3] are programmed to 1, then one error is inserted into the G1 byte for that particular
STS-1(s) each time the microprocessor interface block SMPR_BER_INSRT
The TMUX provides a protection switch MUX for REI-P insertion. The MUX is controlled by TMUX_TPREIRDISEL
(Table 107 on page
the protection board rather than from the receive side of the same TMUX.
390
Bit 3
0
0
0
0
1
1
1
1
109), the TMUX sends a 3-bit code that conforms to the earlier 1-bit version of the standards. If
describes the encoding of the path RDI defects.
) is written into the corresponding three STS-1 G1 byte output bits (G1[3:1]). For STS-3 mode, each
Bit 2
G1
0
0
1
1
0
0
1
1
103). If TMUX_TPREIRDISEL = 1, then the RDI-P value for insertion is taken from the value on
103). If TMUX_TPREIRDISEL = 1, then the REI-P value for insertion is taken from the value on
Bit 1
(Table
0
1
0
1
0
1
0
1
(Table 108 on page
115) to 1. For STM-1 mode, only TMUX_TPREIINS[1] is relevant. If the register
(continued)
LCD-P, PLM-P (LCD-P not supported in Super Mapper).
105), then data from TMUX_TRDIPINS[1—3][2:0]
AIS-P, LOP-P (nonenhanced RDI-P mode).
AIS-P, LOP-P (nonenhanced RDI-P mode).
TIM-P, UNEQ-P (enhanced RDI-P mode).
No defects (nonenhanced RDI-P mode).
No defects (nonenhanced RDI-P mode).
AIS-P, LOP-P (enhanced RDI-P mode).
No defects (enhanced RDI-P mode).
Triggers
(Table 65 on page66
Agere Systems Inc.
) bit is asserted.
(Table 110 on
May 2001
(Table 114