tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 536

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.26.19 Drive to 3-State and 3-State to Drive Timing
The minimum number of stuff time slots is 3 (in the E1 mode). This allows enough time to switch the bus between
devices. The device on the bus can drive the bus high for one extra clock cycle to ensure a fast rise time. The
device then 3-states while the bus is pulled high, using a pull-up resistor. Optionally, the next device starts driving
early for one clock cycle to ensure that there is minimal delay between the clock and data outputs (the turn-on
delay of the buffer is eliminated by turning on the buffer one clock cycle early). The timing for the case of three stuff
time slots is shown in the
driven to 1.)
See
PSB receive and transmit interface and clock timing parameter specifications.
21.27 Serial Multiplex Interface
The network serial multiplexed interface (NSMI) provides a no-slip capability for transfer of multiple framed DS1s
and/or E1s from one device to another using a very narrow interface. A no-slip interface is widely used in datacom
and IMA applications. There are two NSMI interface modes of operation requiring either six or eight signals to be
used.
Mode 1 uses six primary signals. The six primary signals are composed of three transmit and three receive signals.
The transmit signals are LINETXCLK29 (R24), LINETXDATA29 (T23), and LINETXSYNC29 (R26). The receive
signals are LINERXCLK29 (B13), LINERXDATA29 (D13), and LINERXSYNC29 (A13). Each group of three signals
provide clock, data, and control information.
The data and link number specified by the LINETXDATA29 and LINETXSYNC29 will be received in the same order
by the receive side of the Super Mapper after traversing the switch side of the system.
536
Section 5.6 Parallel System Bus Timing on page 47
DEV 0 ENA
SYS DATA[I]
DEV 1 ENA
SYS CLK
Figure 76. Parallel Bus System Interface Turnaround Timing
Figure
76. (In the receive direction from the switch, we assume the stuff time slots are
HIGH-IMPEDANCE
DEV 0, LINK 0-N
DRIVE
DEV 0 DRIVES
HIG H FOR ONE
EXTR A CLO CK
MINIMUM OF 3 STUFF TIME-SLOTS
CYCLE
R
USING A PULL-UP
in the Timing Characteristics section of this data sheet for
PULLED HIGH
R
HIGH ONE CLOCK
DEV 1 MAY DRIVE
CYCLE EARLY
R
(continued)
HIGH-IMPEDANCE
DRIVE
DEV 1, LINK 0-N
Agere Systems Inc.
May 2001
5-8992(F)