tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 512

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Receive Stack Host Interface. Host access to the shared system stack will be managed using a stack availability
status bit. This bit reflects the stack availability status for each individual port. The host will use this status bit for
each port to determine when the stack is available for reading. Each stack is made unavailable only to enable a
window for the data link block to update the system stack. The window will be large enough so that any small
amount of overlap will not allow the possibility of a collision.
D, Sa, or DDS data link bits are collected over the multiple frame time periods appropriate for each frame type. The
stack is available for reading during that entire time period except for the last frame. During that one frame time, the
internal stack will be switched to the system stack. The stack will be made accessible once the transfer is done,
after which the Rx stack ready status bit will be set.
If the host is managing the stack via interrupts from the data link block and the interrupt can be serviced within
8.8 ms for SLC -96, 3.8 ms for CEPT, or 4.3 ms for DDS, then the host simply reads the stack. If the host is polling
the Rx stack ready status and reading the stack arbitrarily, then the host is required to read the Rx stack available
status bit FRM_RXSA
access the corresponding stack locations. If that bit is set to 0, the host should poll on that bit until it changes.
Stack Available and Stack Ready Bit Formats. As described above, when the stack has been filled, the stack
available bit goes high. One or two frames before the stack is about to be filled, the stack available bit goes low and
stays low for one or two frames. This prevents the host from reading when a pointer switch is about to happen, pre-
venting the host from getting the data mixed. The stack ready bit is set to 1, also, when the stack has been filled.
The host clears this bit.
Receive Stack Pointer. The stack pointer maintains two pointers: an internal pointer and a host pointer. The
pointer identifies which stack is active for the host and which stack is active for the internal logic. These pointers will
always point to opposite stacks. When the TDM interface block is writing Sa bits or D bits to the stack, then the
internal pointer may be selecting the upper stack. In this case, the host pointer is selecting the lower stack for the
host reads. At the beginning of each double multiframe or each superframe, a pointer switch takes place. This
switch takes place during the time in which the host is prevented from accessing the stack for a particular link.
A stack pointer is maintained for each of the links individually.
512
Sr bit
(HOST CLEARS THIS BIT WHENEVER)
Sa bit
(Table
Figure 62
Figure 62. Stack Available and Stack Ready Bit Formatting
406) which corresponds to the respective port. If that bit is set to 1, then the host can
SLC -96: 70 FRAMES (8.75 ms)
CEPT: 30 FRAMES (3.75 ms)
DDS:
shows the dynamics of these bits.
35 FRAMES (4.4 ms)
ONE STACK OF DATA
2 FRAMES
2 FRAMES
1 FRAME
(continued)
(0.125 ms)
(0.25 ms)
(0.25 ms)
SET HIGH HERE
STACK NOT AVAILABLE
NEXT STACK
Agere Systems Inc.
May 2001
5-9026(F)r.1