tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 411

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
18 SPE Mapper Functional Description
Whenever the continuous N-times detect signals are defined, they require not only that the monitored signal be
consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status
can be updated. If there are any errors in the framing pattern, then the consecutive N-times detection counters
must be reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set the
CNTD to 1 time detect.
18.14.1 Loss of Clock and Loss of Sync Monitors
The SPE mapper detects and reports loss of the input clocks state for RLSCLK (pin V4) (19 MHz clock) in bit
SPE_RLSLOC
DS3DATAINCLK (pin J22) (DS3 external clock) in bit SPE_RDS3LOC
stuck low for time T. The detection time T will be greater than 10 µs but less than 125 µs. The function uses the
microprocessor clock as its reference. The device will report changes in the states using bits, SPE_RLSLOCD
(Table 146 on page
SPE_RLSLOCM
respectively.
The SPE mapper will detect loss-of-sync conditions for the telecom bus sync signals. The states are reported in the
bits, SPE_RSY52LOS
SPE_RV1LOS
SPE_RJ0J1V1LOSD
SPE_RSY52LOSM
SPE_RV1LOSM
18.14.2 J1 Monitor
J1 (path trace) monitoring has six different monitoring modes controlled by bits SPE_J1MONMODE[2:0]
(Table
Agere Systems Inc.
SPE_J1MONMODE[2:0] = 000: the SPE mapper will latch the value of the J1 byte every frame for a total
64 bytes in SPE_RJ1DMON[1—64][7:0]
next expected value (the expected value is obtained by cycling through the previous stored 64 received bytes in
round-robin fashion) and setting the path trace identifier state bit, SPE_RTIM
in state is reported in bit, SPE_RTIMD
checked by the hardware.
SPE_J1MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for
0x0DA characters
is continuously written into SPE_RJ1DMON[1—64][7:0] with the first byte residing at the first address. If any
received byte does not match the previously received byte for its location, then the state bit SPE_RTIM is set.
Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.
SPE_J1MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most sig-
nificant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of
operation is the same as in SONET framing mode.
SPE_J1MONMODE[2:0] = 011: a new J1 byte (SPE_RJ1DMON[1][7:0]) will be detected after a number of con-
secutive consistent occurrences (SPE_CNTDJ1[3:0]
changes to this byte is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM. The delta bit in this
mode indicates a change in state for the J1 byte, and the bit SPE_RTIM is not used.
SPE_J1MONMODE[2:0] = 100: the user will program the 64 expected values of J1 in registers,
SPE_RJ1DEXP[1—64][7:0]
ing the 0x0A character, is written into the first register location, SPE_RJ1DEXP[1][7:0]. The SPE mapper com-
pares the incoming J1 sequence with the stored expected value, setting the SPE_RTIM state bit if they are
different. Any changes in the state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.
149):
(Table
(Table 148 on page
(Table
(Table
134), SPE_RC52LOCD
(Table
to indicate that the next byte is the first byte of the path trace message. The J1 byte message
(Table
148). The device will report changes in the states in bits SPE_RSY52LOSD
(Table
147), respectively.
147), SPE_RC52LOCM
147), SPE_RJ0J1V1LOSM
146), SPE_RSPELOSD
148), SPE_RJ0J1V1LOS
(Table
137), RLSC52 (pin AC2) (52 MHz clock) in bit SPE_RC52LOC
164), in SONET framing mode, where the first expected byte, the byte follow-
(Table
(Table
(Table
146), using interrupt mask bit SPE_RTIMM
(Table
162). The SPE mapper compares the incoming J1 byte with the
146), and SPE_RDS3LOCD
(Table
(Table
(continued)
(Table
147), and SPE_RDS3LOCM
(Table
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
146), SPE_RV1LOSD
147), SPE_RSPELOSM
150)) of a new pattern in the J1 overhead byte. Any
148), SPE_RSPELOS
(Table
TMXF28155/51 Super Mapper
148), as determined by stuck high or
(Table
(Table
(Table
(Table 147 on page136
(Table
148), if different. Any change
(Table
146); interrupt mask bits
146); interrupt mask bits
(Table
148), and
0x0D and then the
147), and
147). CRC is not
(Table
(Table
148), and
146),
),
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