tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 371

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
(continued)
17.5.7 F1 Monitor
The TMUX monitors the fault location byte TMUX_RF1MON0[7:0]
(Table 101 on page
100). A new fault location
state will be detected after the number of consecutive consistent occurrences of a new pattern in the F1 overhead
byte as determined by the value programmed in TMUX_CNTDF1[3:0] (
Table 98 on pag
e98).
The TMUX maintains a history of the previous, valid F1 byte in TMUX_RF1MON1[7:0]
(Table 101 on pag
e100),
and any changes will be reported via TMUX_RF1MOND (delta state)
(Table 82, starting on pag
e79) and
TMUX_RF1MONM— (interrupt mask)
(Table 86 on page88
).
This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame
state.
17.5.8 B2 BIP-8 Check
A B2 BIP-8 even parity is computed over all the incoming bits (except for the nine section overhead bytes) of the
STS-1 frame after descrambling, and compared to the B2 byte received in the next frame. The total number of B2
BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB2;
Table 94 on page
94), is counted.
Upon the assertion of the performance monitor control signal as configured in the microprocessor interface, the raw
count will be reset to zero and the value transferred to an 18-bit holding register for B2 error counts
(TMUX_B2ECNT[17:0]; see
Table 125 on page119
). In case of overflow, depending on the value programmed in
the microprocessor interface register bit SMPR_SAT_ROLLOVER
(Table 67 on pag
e68), the B2 error counter will
either roll over or saturate at the maximum value until cleared.
17.5.9 Automatic Protection Switch (APS) Monitor
The TMUX monitors the receive APS value (the K1 byte, and the five most significant bits of the K2 byte) and
stores this value in TMUX_RAPSMON[12:0]
(Table 102 on page100
). This register is updated after the reception
of a programmed number of identical consecutive frames as determined by the value in TMUX_CNTDK1K2[3:0]
(Table 98 on page98
). Whenever the contents of TMUX_RAPSMON[12:0] changes, a delta bit,
TMUX_RAPSMOND will be set
(Table 82, starting on page
79) and the interrupt can be masked using
TMUX_RAPSMONM
(Table 86 on pag
e88). This indication also contributes to a separate device interrupt indica-
tion specifically intended for automatic protection switching.
The TMUX monitors this same 13-bit APS value (K1[7:0], K2[7:3]) in the receive direction and reports when the
APS value is inconsistent, using TMUX_RAPSBABE—Receive APS Babble Event
(Table 82 on pag
e79) and
TMUX_RAPSBABM—Receive APS Babble Mask
(Table 86 on page
88). Inconsistent APS bytes are defined as
the number of successive frames of ASP data where no frames satisfy the criteria for updating the
TMUX_RAPSMON register
(Table 102 on page100
). The number of inconsistent frames allowed before reporting
is programmed in TMUX_CNTDK1K2FRAME[3:0] (default = 12, see
Table 98 on page98
). This continuous N-
times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state or upon the
detection of a B1 error.
17.5.10 K2 Monitor, AIS-L and RDI-L Detect
The three least significant bits of K2 are independently monitored and the current value is stored in
TMUX_K2MON[2:0]
(Table 102 on page100
). The register will be updated after the programmed number of con-
secutive identical K2[2:0] bits. This number is programmed by the value in TMUX_CNTDK2[3:0]
(Table 98 on
page
98). Whenever the contents of TMUX_K2MON[2:0] changes, a delta bit, TMUX_RK2MOND will be set
(Table 82, starting on page79
), and the interrupt can be masked using TMUX_RK2MONM
(Table 86 on pag
e88).
The TMUX monitors for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits (K2[2:0] = 111). When line AIS is detected,
TMUX_RLAISMON
(Table 91 on page92
) will be set to 1 after a number of consecutive occurrences of line AIS as
determined by the value programmed in TMUX_CNTDK2[3:0]. Once set, AIS-L will be cleared after a number of
consecutive frames of no line AIS as determined by this same value in TMUX_CNTDK2[3:0].
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