tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 476

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Contents
476
21.18 Transmit Signaling Status Registers ...................................................................................................... 502
21.19 Performance Monitoring Functional Integration into Superframer ......................................................... 503
21.20 Performance Report Message ............................................................................................................... 506
21.21 Performance Monitoring References/Standards .................................................................................... 508
21.22 Facility Data Link .................................................................................................................................... 508
21.23 HDLC Functional Description ................................................................................................................. 517
21.24 HDLC Operation .................................................................................................................................... 517
21.25 Framer Phase-Lock Loop (PLL) ............................................................................................................. 522
21.26 System Interface .................................................................................................................................... 523
21.17.2 Support of Byte Sync SONET Mapping .................................................................................... 502
21.18.1 Maintenance of CEPT Related Status Bits ................................................................................ 502
21.22.1 Facility Data Link References/Standards .................................................................................. 508
21.22.2 Receive Data Link Functional Description ................................................................................. 509
21.22.3 SLC -96 Superframe Receive Data Link .................................................................................... 509
21.22.4 DDS Receive Data Link Stack ................................................................................................... 509
21.22.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack ..... 510
21.22.6 Receive Data Link Stack Idle Modes ......................................................................................... 511
21.22.7 Receive Data Link Stack Pointer ............................................................................................... 511
21.22.8 Transmit Facility Data Link Functional Description ................................................................... 513
21.22.9 SLC -96 Superframe Transmit Data Link ................................................................................... 513
21.22.10 DDS Transmit Data Link Stack ................................................................................................ 514
21.22.11 Transmit ESF Data Link Bit-Oriented Messages ..................................................................... 515
21.22.12 CEPT, CEPT Multiframe Transmit Data Link Sa bits Stack .................................................... 515
21.22.13 Transmit Data Link Stack Idle Modes ...................................................................................... 516
21.22.14 SLC -96, DDS, or CEPT ESF Frame Alignment ...................................................................... 516
21.24.1 Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing) ................................................................... 517
21.24.2 Flags .......................................................................................................................................... 517
21.24.3 Aborts ........................................................................................................................................ 518
21.24.4 Receive IDLES .......................................................................................................................... 518
21.24.5 CRC ........................................................................................................................................... 518
21.24.6 HDLC Mode ............................................................................................................................... 519
21.24.7 Receive HDLC Transparent Mode ............................................................................................ 519
21.24.8 Receive HDLC ........................................................................................................................... 519
21.24.9 Receive HDLC Features ........................................................................................................... 519
21.24.10 Transmit HDLC FIFO Features ............................................................................................... 520
21.25.1 Framer Timing Selection ........................................................................................................... 523
21.26.1 System Interface Introduction .................................................................................................... 523
21.26.2 System Interface References/Standards ................................................................................... 524
21.26.3 Transmit/Receive System Interface Features ........................................................................... 524
21.26.4 Double NOTFAS System Time-Slot (FRM_DNOTFAS (Table 347)) Mode .............................. 524
21.26.5 Transparent Mode ..................................................................................................................... 525
21.26.6 Loopbacks ................................................................................................................................. 525
21.26.7 System AIS ................................................................................................................................ 525
21.26.8 Slip Detection ............................................................................................................................ 526
21.26.9 The Concentration Highway (CHI) Mode .................................................................................. 526
21.26.10 Nominal CHI Timing ................................................................................................................ 526
21.26.11 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled .............................. 528
21.26.12 CHI Timing with Associated Signaling Mode Enabled ............................................................ 529
21.26.13 ASM 2-Byte Time-Slot Format ................................................................................................ 529
21.26.14 CEPT: Time-Slot 16 Signaling ASM 2-Byte Time-Slot Format ................................................ 530
21.26.15 CHI Offset Programming ......................................................................................................... 530
Table of Contents
(continued)
(continued)
Agere Systems Inc.
May 2001
Page