tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 450

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description
19.14.5 VT Multiplexer (VTMUX)
The VTMUX logic block (in
data onto the outgoing mapper transmit path data bus.
Bits VT_TX_GRP_TYPE[6:0]
VT1.5/TU-11 or a VT2/TU-12.
See
19.14.6 Transmit Signaling (TX_VTSIG)
The TX_VTSIG logic block (in
phase and data from the framer and insert it into the outgoing VT/TU.
Note: This block is only enabled when operating in the byte synchronous mode.
Table 574. Framing Byte Generation Per Channel
* X—value based on SMPR_OH_DEFLT
19.14.7 Transmit Lower Path Overhead (TX_LOPOH)
The TX_LOPOH logic block (in
low-order path overhead as well as the REI and RDI values from the external LOPOH serial access channel. The
following functions are supported:
450
VT_USE_FBIT[1—28]
The signaling is received from the appropriate framer link selected with the value programmed in bits
VT_TXSIG_CH_SEL[1—28][4:0]
routing information programmed within the cross connect (XC) block.
The TX_VTSIG block determines whether the phase and signaling bits are to be used in the VT/TU mapping. If
the phase or signaling bits are not being used (VT_USE_PBIT[1—28] = 0, VT_USE_SBIT[1—28] = 0
(Table
Stomping of the F bit is controlled by VT_USE_FBIT[1—28] = 0
gramming signaling inserting.
The TX_LOPOH logic block retimes all incoming signals on the falling edge of the external input pin
LOPOHCLKIN (AC13).
The source of the external inputs LOPOHDATAIN (AC14), LOPOHVALIDIN, and LOPOHCLKIN is required to
hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The TX_LOPOH logic block monitors
the incoming LOPOHVALIDIN and detects failure conditions. A failure exists if there are less than eight
LOPOHCLKIN cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the internal bit
counter reaches its maximum count, for the active data type, and LOPOHVALIDIN does not transition to 0.
(See
Table 551
202)), they will be set to SMPR_FXD_STFF_DEFLT
Table
0
0
0
0
1
1
1
1
through
202.)
Table 554
VT_USE_PBIT[1—28]
Figure 39 on page429
(See
(Table
Figure 39 on page429
Figure 39 on page
(Table
Table
on
(Table
0
0
1
1
0
0
1
1
180) are programmed to determine whether the outgoing tributary is a
page 430
67), R—value based on SMPR_FXD_STFF_DEFLT (
202.)
202). VT_TXSIG_CH_SEL[1—28][4:0] is a necessary duplication of the
through
VT_USE_SBIT[1—28]
) performs all functions necessary to place the appropriate VT
429) performs all necessary functions to receive and store the
(See
) will perform all necessary functions to retrieve the signaling
page 431
(continued)
Table
0
1
0
1
0
1
0
1
(Table
202.)
for VT/TU mapping formats.
(Table
67) in the microprocessor interface block.
202). Refer to
VT/TU frame byte* = XXXXXXXR
VT/TU frame byte* = XXS1S2S3S4XR
VT/TU frame byte* = P1P0XXXXXR
VT/TU frame byte* = P1P0S1S2S3S4XR
VT/TU frame byte* = XXXXXXFR
VT/TU frame byte* = XXS1S2S3S4FR
VT/TU frame byte* = P1P0XXXXFR
VT/TU frame byte* = P1P0S1S2S3S4FR
Table
67).
Table 574
Action
Agere Systems Inc.
below for pro-
May 2001