tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 404

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
18.9.1 DS3 M13
The SPE mapper is configured to/from the M13 MUX/deMUX as the source/destination of data by setting bits,
SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 00 or 01.
18.9.2 DS3 Loopback Channel
The DS3 loopback circuit is placed in the SPE mapper to allow demapping and remapping of a DS3 signal.
When SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 10, the SPE mapper extracts the asynchronous DS3
data and clock from the received payload. The recovered DS3 is looped back to the transmit path and either
mapped as AU-3/STS-1 SPE signal for the North American digital systems or mapped as TUG-3 for the European
digital systems. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to
be remapped as a TUG-3 signal or vice versa.
18.9.3 DS3 Clear Channel from External Pins
The SPE mapper is configured for a DS3 signal at 44.736 MHz rate from external device pins by setting
SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 11.
The DS3 data can either be unipolar or bipolar. Unipolar data and clock is selected (device pins DS3POSDATAIN,
DS3DATAINCLK, DS3POSDATAOUT, and DS3DATAOUTCLK (pins M22, J22, R22, and N22, respectively)) when
bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 0
pins DS3POSDATAIN, DS3NEGDATAIN, DS3DATAINCLK, DS3POSDATAOUT, DS3NEGDATAOUT, and
DS3DATAOUTCLK (pins M22, K22, J22, R22, P22, and N22, respectively)) when bits SPE_TDS3_BIPOLAR and
SPE_RDS3_BIPOLAR = 1.
When bipolar data is selected for the transmit path (SPE_TDS3_BIPOLAR = 1), the data received from the external
pins is expected to be B3ZS encoded. A B3ZS decoder is used to recover the DS3 data prior to being mapped into
a container.
The B3ZS decoder also checks for bipolar coding violations. The SPE mapper contains a counter that increments
on each occurrence of a received bipolar coding violation (BPV). It also monitors the occurrence of excessive zeros
(EXZ), which is defined as any zero string length equal to or greater than three. These are part of the performance
monitoring counters that can be sampled and simultaneously reset. Their last sampled values are available through
SPE_BIPOL_CNT[23:0] and SPE_EXZ_CNT[23:0]
When bipolar data is selected for the receive path (SPE_RDS3_BIPOLAR = 1), the data out from the external pins
will be B3ZS encoded. A single bipolar violation may be inserted in the data when SPE_BIPOL_ERR is asserted
(Table
The clock edge for sampling the transmit path data (device pin DS3DATAINCLK (pin J22)) is selected with
SPE_TDS3CLK_EDGE
18.10 Phase Detector for External DS3 PLL
The receive section of the SPE mapper has a phase detector circuit built inside the device. This phase detector cir-
cuit generates the necessary up and down signals (device pins PHASEDETUP and PHASEDETDOWN (pins V22
and U22, respectively)) for an external phase-lock loop (PLL) circuit to generate a smooth DS3 clock at
44.736 MHz rate.
The logic sense of the phase detector up and down outputs may be inverted with bits SPE_PHDETUP_INV
(Table
404
145).
153) and SPE_PHDETDN_INV, respectively.
(Table
153).
(Table
(continued)
160).
(Table
153). Bipolar data and clock is selected (device
Agere Systems Inc.
May 2001