tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 526

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.26.8 Slip Detection
Controlled slips are performed on frame boundaries. Elastic store slip overflow and underflow is monitored with sta-
tus bits FRM_SLIPO and FRM_SLIPU
repeated. In the case of an overflow, an entire frame in skipped.
21.26.9 The Concentration Highway (CHI) Mode
This is the system interface on Agere’s framers. It can be programmed to operate at 2.048 MHz, 4.096 MHz,
8.192 MHz, or 16.384 MHz clock rates (data rates up to 8.192 Mbits/s only). In this mode, a pair of global system
clock and system frame sync (one for the transmit and one for the receive direction) is required. The offset between
the frame sync and bit 0 of time slot 0 is programmable in this mode.
interface operating in the CHI mode. The data path (shown in bold arrows) passes through the slip buffer. Slips in
the form of buffer overflows or underflows are detected and reported in this mode. This interface can be used, for
example, to interface with the time slot interchange (TSI) device.
21.26.10 Nominal CHI Timing
Figure 70
(ASM) is disabled. The frames are 125 s long and consist of 32 contiguous time slots when the 2.048 MHz data
rate mode is selected.
In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots.
In CEPT frame modes, the CHI frame consists of 32 payload time slots:
TCHIDATA—output data to system.
RCHIDATA—input data to system.
TCHIFS—transmit CHI frame sync.
RCHIFS—receive CHI frame sync.
526
TRANSMIT PATH
RECEIVE PATH
ALIGNER
FORMATTER
illustrates nominal CHI frame timing. Double time slot mode (CHIDTS) and associated signaling mode
FRAME
FRAME
TDM
28
Figure 69. CHI Mode of the Transmit System Interface
(Table 393 on page285
28
TDM
FANOUT
BUFFER
1
SLIP
TCLK
TFS
). In the case of an underflow, an entire frame is
ADAPTATION
BUFFER
RATE
Figure 70
PLL
(continued)
below shows the transmit system
RECEIVE SYSTEM
TRANSMIT SYSTEM
28
RS_D[28:1]
RS_G
RS_GCLK
RS_GTCLK
TS_GFS
TS_GCLK
TS_D[28:1]
Agere Systems Inc.
TO
CROSSCONNCT
BLOCK (XC)
May 2001
5-9032(F)