tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 598

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
26 Applications
In the byte-sync mode, the frame sync and signaling (VT SPE) information are also passed to the mapper. In the
receive direction, the mapper block provides the line data, line clock, frame sync (byte-sync mode), and signaling
information (byte-sync mode) to the superframer. Performance reports, in the form of HDLC packets (PRMs), are
sent from the receive performance monitor block to the transmit HDLC block.
Figure 106. Super Mapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled
598
INTERFACE
INTERFACE
TRANSMIT
RECEIVE
SYSTEM
SYSTEM
SUPER MAPPER: FRAMER
(continued)
(EXTRACTION)
PROCESSOR
SIGNALING
PROCESSOR
(INSERTION)
SIGNAL
SIGNALING STOMP
RECEIVE
HDLC
DATA
(EXTRACTED FROM SYSTEM
(TO SIGNALING REGISTERS)
TRANSMIT SIGNALING DATA
OF SIGNALING REGISTERS)
PERFORMANCE
RECEIVE SIGNALING DATA
TRANSMIT
MONITOR
FACILITY DATA
HDLC
FACILITY DATA
TRANSMIT
RECEIVE
LINK
LINK
ESF PRM PATH
FORMATTER
TRANSMIT
RECEIVE
ALIGNER
FRAME
FRAME
CONNECT
MAPPER
FRAMER
CROSS
DS1
TO
ROBBED-BIT SIGNALING
BYTE-SYNCHRONOUS
ROBBED-BIT SIGNALING
Preliminary Data Sheet
BYTE-SYNCHRONOUS
RECEIVE DATA
VT MAPPER:
TRANSMIT DATA
VT MAPPER:
M12 MULTIPLEXER
SUPER MAPPER
SUPER MAPPER
VT MAPPER
INTERFACE
INTERFACE
Agere Systems Inc.
May 2001
5-8928(F)