tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 560

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
22 Cross Connect (XC) Block Functional Description
The register XC2_DS2M12CLK SOURCE ID is defined as:
The register can be programmed to route DS2 clocks from various sources based on the following table:
22.7.3 M12 DeMUX (Receive Path)
The M12 deMUX disassembles a DS2 into three E1s or four DS1s. The routing of DS2 data and clocks to M12
DeMUX is controlled by the register XC2_M21_SRC[1:7] which are defined as:
The routings are based on the following table.
When bits 7—5 of XC2_M21_SRC set to 100, the user also needs to set bits 7—5 of the related register
XC_ALCO_SOURCE_ID(I) to 001 as well as the appropriate channel value to ensure the demand clocking opera-
tion.
The DS2 input has six connection options as shown in
The external I/O inputs for DS2 clock and data are cross connected by programming bytes, XC2_M21[1—7][7:0]
(Table
The channel select value of 1 to 7 selects DS2 data from device pins LINETXSYNC[15] to LINETXSYNC[21] and
selects DS2 clock from LINETXSYNC[22] to LINETXSYNC[28], respectively.
A DS2 signal loopback may be performed for the M12 MUX/deMUX by programming the XC2_M21[1—7][7:0]
(Table
connecting among the seven channels is supported. For example, the output of M12 MUX 1 may be connected to
the input of M12 deMUX 5.
The TPG may be cross connected to the M12 deMUX DS2 inputs by programming the XC2_M21[1—7][7:0] byte in
the XC2_M12_SRC[1—7] registers with a source2 ID = 00 and a channel ID = 4. The connection is not useful
because the DS2 pattern generator is limited to sending unframed pseudorandom data patterns that cannot be
demultiplexed into DS1s or E1s.
560
SOURCE2_ID
SOURCE2_ID
SRC2_BLK
SRC2_BLK
Others
000
001
010
011
100
101
459) in configuration registers XC2_M12_SRC[1—7], with a source2 ID = 11 and a channel select of 1 to 7.
459) byte in the XC2_M12_SRC[1—7] registers with a source2 ID = 01 and a channel select of 1 to 7. Cross
Bit
00
01
10
11
Bit
CHANNEL2_ID
CHANNEL2_ID
7
0
7
Don’t care
Don’t care
1 to 29
1 to 29
1 to 29
1 to 29
1 to 7
1 to 7
1 to 7
1 to 7
4
SRC2_BLK[2:0]
SRC2_BLK[2:0]
6
6
DS2DATA/CLK from Pin LINETXSYNC[21:15]/LINETXSYNC[28:22]
DS2DATA/CLK from Pin LINERXDATA[29:1]/PIN_DS2_AISCLK
5
5
DS2DATA/CLK from Pin LINERXDATA/CLK[29:1]
DS2 Clocks Sourced from LINETXSYNC[8:14]
Figure 90 on page561
DS2 Clocks Sourced from PIN_DS2_AISCLK
DS2 Clocks Sourced from LINERXCLK[1:29]
DS2 Clocks Sourced from LINETXCLK[1:29]
DS2DATA/CLK from M23 DEMUX
4
4
DS2DATA/CLK from M12 MUX
DS2DATA/CLK from TPG
Function
Function
Not Valid
3
3
(continued)
CHANNEL2_ID[4:0]
CHANNEL2_ID[4:0]
.
2
2
Agere Systems Inc.
1
1
May 2001
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