tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 260
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tmxf28155
Manufacturer Part Number
tmxf28155
Description
Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
Manufacturer
ETC-unknow
Datasheet
1.TMXF28155.pdf
(606 pages)
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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table 353. FRM_SYSGR7, System Interface Global Register 7 (COR)
Table 354. FRM_SYSGR8, System Interface Global Register 8 (R/W)
Table 355. FRM_SYSGR9, System Interface Global Register 9 (R/W)
260
Address
0x80150
Address
Address
0x80056
0x80057
12:0
Bit
15
14
13
15:1
15:1
Bit
Bit
0
0
FRM_RS_DPAR Receive PSB Data Parity Select. This bit is only applicable in
FRM_RS_SPAR Receive Signaling Parity Select. This bit applies to the sig-
FRM_RFSCKE System Interface Receive Frame Sync Clock Edge Select.
FRM_PSB_FS_IM Transmit PSB Frame Sync Interrupt Mask. A 1 pre-
FRM_TPSB_FS_IS
Name
—
Name
—
Name
—
the parallel system bus interface mode. Otherwise, it should
be set to 0.
0 = Odd data parity is expected by the receive system.
1 = Even data parity is expected by the receive system.
naling information in the parallel system bus mode. It also
determines the parity for CHI ASM mode. Otherwise, it should
be set to 0.
0 = Odd signaling parity is expected by the receive system.
1 = Even signaling parity is expected by the receive system.
0 = Receive frame sync (and data) is sampled on the falling
edge of receive clock.
1 = Receive frame sync (and data) is sample on the rising
edge of receive clock.
In parallel system bus mode, this bit also determines the clock
edge used to sample data.
In CHI mode, the sample point of frame sync defines the zero
offset for the CHI.
Reserved. Must write to 0.
Reserved. Must write to 0.
vents the FRM_TPSB_FS_IS
causing an interrupt. A 0 allows the interrupt.
(continued)
Reserved. Must write to 0.
Transmit PSB Frame Sync Error Interrupt. A 1 indi-
cates a frame sync error was detected in PSB mode.
The frame sync was either detected when it should
not have been (misplaced) or was not detected when
it should have (missing). This bit is cleared on read/
write unless the condition that set it still exists after
the read.
Function
Function
Function
(Table
353) status from
Agere Systems Inc.
May 2001
Default
Reset
Default
Default
Reset
Reset
0
1
0x0
0
0
0
0
0
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