tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 28

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Table 14. Microprocessor Interfaces
28
AC24, AD25,
AD26, AE25,
AA22, AC22,
AE22, AD21,
AE21, AC21,
AE20, AC20,
AD20, AF20,
AD19, AF19,
AB25, AA24,
AA25, AA23,
AB23, AC26,
AE19, AC19
W24, W26,
W25, W23,
Y24, Y26,
Y25, Y23,
V24, V26,
U24, U25
V25, V23
AE17
AD17
AC18
AE18
AD18
AF18
Pin
ADDR[19:0]
DATA[15:0]
MPMODE
PAR[1:0]
Symbol
MPCLK
ADSN
RWN
CSN
DSN
(continued)
Type
—
—
—
—
—
—
—
—
—
Pull up
I/O
I/O
I/O
I
I
I
I
I
I
I
Processor Clock. This is the synchronous microprocessor
clock (when MPMODE=1). The maximum clock frequency is
66 MHz. This clock is required to properly sample address,
data, and control signals from the microprocessor in both
asynchronous and synchronous modes of operation. This
clock must be within the range of 16 MHz—66 MHz.
Control Port Mode. If the microprocessor interface is syn-
chronous, CPM should be set to 1. If the microprocessor
interface is asynchronous, CPM should be set to 0.
Chip Select. Active-low chip select. For synchronous mode,
it should be stable beyond a certain setup time before the ris-
ing clock edge when AS is active. For asynchronous mode, it
should be stable before DS is asserted.
Address Strobe. Active-low address strobe that is a 1 PCK
cycle wide pulse for synchronous mode and active for the
entire read/write cycle for asynchronous mode. Address bus
signals, A(19:0), are transparently latched into Super Mapper
when AS is low. The address bus should remain valid for the
duration of AS.
Read/Write Cycle Selection. RW is set high for a read oper-
ation, or set low for write operation.
Data Strobe. DS is not used for synchronous mode. For
asynchronous mode, write operation, DS becomes active
after data is stable. For read operation, it is similar to AS.
Address (19:0). A19 is the most significant and A0 the least
significant bit for addressing all the internal SM registers dur-
ing CPU access cycles.
Note: The Super Mapper is little endian, the least significant
Data (15:0). Data bus for all transfers between the CPU and
the internal SM registers. The pins are inputs during write
cycles and outputs during read cycles. DATA15 is the MSB
and DATA0 is the LSB.
CPU Port Parity (1:0). Byte-wide parity bits for data. CPP[1]
is the parity for D[15:8] and CPP[0] is the parity for D[7:0].
byte is stored in the lowest address and the most sig-
nificant byte is stored in the highest address. Care
must be exercised in connection to microprocessors
that use big-endian byte ordering.
Description
Agere Systems Inc.
May 2001