tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 262

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
12.6 Signaling Global Registers
Table 359. FRM_SGR1, Receive Signaling Global Register 1 (R/W)
Table 360. FRM_SGR2, Receive Signaling Global Register 2 (R/W)
262
Address
Address
0x80061
0x80060
14:10
14:10
Bit
9:0
8:6
5:2
Bit
15
15
9
1
0
FRM_R_SCOSEN Receive Signaling Change of State FIFO Enable. When set
FRM_R_LINKCNT[4:0] Receive Link Count. Indicates the number of links ser-
FRM_TEST_BIT[2:0]
SCOSDTH[9:0]
FRM_R_TSAISHG
FRM_R_AFZFBE
FRM_R_
Name
—
Name
—
—
—
to 1, this configuration bit enables the maintenance of the sig-
naling change of state FIFO. When set to 0, no entries will be
made into the FIFO. This bit applies to all of the links. If an
individual time slot is programmed for no signaling, then no
entries will be made for that time slot. Also, if the signaling
source in the receive path is set to host, then no entries will be
made for that time slot.
Reserved. Must write to 0.
Receive Signaling Change of State FIFO Depth Threshold.
This number can be programmed from 0 to 672. If the number
of entries in the signaling change of state FIFO exceeds the
value programmed here, then the associated interrupt status
bit will be set.
(continued)
System AIS for Handling Groups. When set to 1, this
configuration bit forces AIS to the system interface for
those signaling bits which correspond to a handling group,
which is out of alignment. A 0 disables this feature. This
feature is only applied to those links which are enabled for
byte sync mapping and handling groups using the per-link
signaling configuration registers.
viced by the signaling block. This value should be set to 28
when the Super Mapper is interfacing with only DS1 links;
it should be set to the actual number of links active for
mixed mode applications.
Reserved. Must write to 0.
Test Bits.
Reserved. Must write to 0.
Automatic Signaling Freeze on Framing Bit Errors. Set
to 1 in order to freeze signaling register updates based on
framing bit errors.
Reserved. Must write to 0.
Function
Function
Agere Systems Inc.
May 2001
Default
Default
Reset
Reset
000
28
0
0
0
0
0
0
0