tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 452

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description
* Maximum gap between rising clock edges = 1386 ns.
19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface)
The VT mapper input clock and data will meet the timing requirements of G.703, 1.544 MHz ± 50 ppm and
2.048 MHz ± 50 ppm. The VT mapper will accommodate up to ± 200 ppm to allow operation under maintenance or
trouble conditions. The clock edge to retime the data is programmable with VT_TX_CLKEDGE[1—28] bit
(Table
edge when VT_TX_CLKEDGE[1—28] = 0.
See
19.16 VT Mapper Lower-Order Path Overhead Interface Timing
19.16.1 VT Mapper Receive Path Overhead Interface Description
452
Figure 45
LOPOHVALIDOUT
LOPOHDATAOUT
LOPOHCLKOUT
VT Mapper Timing on page 45
VTMPR_RFSYNC
VTMPR_RDATA
198). The receive data is clocked on the rising edge when VT_TX_CLKEDGE[1—28] = 1 and the falling
VTMPR_RCLK
contains the VT mapper receive path overhead serial channel format and timing.
0 0 1
TMUX/SPEMPR RDI/REI
Figure 45. VT Mapper Receive Path Overhead Serial Access Channel
TS #0
154 ns
TS #1
for VT mapper interface and clock timing numbers.
VTMPR VT#1—28 V5(MSB–>LSB)
0 1 0
MINIMUM OF 8 CYCLES
Figure 44. E1 Interface
462 ns
125 s
FRAME #1 OF MULTIFRAME
(continued)
VTMPR VT#1—28 J2(MSB–>LSB)
125 s
0 1 1
924 ns*
154 ns
VTMPR VT#1—28 Z6(MSB–>LSB)
1 0 0
TS #1
Agere Systems Inc.
TS #1
May 2001
5-8989(F)r.1
5-8327(F)r.2