tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 439

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description
19.12 Receive Signaling (RX_VTSIG)
The RX_VTSIG logic block (in
the received signaling bits when operating in DS1 byte-synchronous mode. The following features are imple-
mented:
Table 556. Rx Signaling Behavior per Channel
* If the P1 and P0 bits are not used for phase indication and the F bit is not passed transparently, the F bit is overwritten with the appropriate SF
† When operating in the ESF mode, the Ft bits will be overwritten with the ESF frame and the C and M bits passed transparently.
Agere Systems Inc.
or ESF framing pattern based on a random starting position. Robbed-bit signaling will not be accessible under such a condition.
Unless bit
eration.
Any change in state of
Unless the
The signaling is sent to the appropriate framer link selected by bits VT_RXSIG_CH_SEL[1—28][4:0] (
VT_RXSIG_CH_SEL[1—28][4:0] is a necessary duplication of the routing information programmed within the
cross connect (XC) block.
When VT_SYNC_PBIT[1—28] = 1
ing VT/TU phase indication (P1, P0). Otherwise, VT_LOPS[1—28]
(Table
P-bit phase synchronization (VT_LOPS[1—28] = 0) is declared following two consecutive nonerrored multi-
frames (48 frames). Loss of phase synchronization (VT_LOPS[1—28] = 1) is declared following the number of
consecutive errored multiframes programmed in bits VT_LOPS_NTIME[3:0]
VT_LOPS[1—28] state will be detected and reported to the microprocessor with bit VT_LOPS_D[1—28].
If the loss of phase synchronization (VT_LOPS[1—28] = 1) condition exists and VT_LOPS_AIS_INH = 0, DS1
AIS is transmitted downstream and the signaling bits will be forced to the value in SMPR_OH_DEFLT
in the MPU block. Otherwise (VT_LOPS[1—28] = 0), the VT_RX_VTSIG logic block will behave as described in
Table 556
Unless VT_LOPS_M[1—28]
See
VT_SYNC_PBIT
(Table
Table 556
[1—28]
169) will be forced to 0.
0
0
0
1
1
1
204)
VT_
below.
VT_
J2TIM_AIS_INH
below for signaling behavior based on the receive status and control.
J2TIM_M[1—28]
VT_WR_FBIT
(Table
VT_
[1—28]
X
0
1
1
1
1
J2TIM[1—28][1—16][7:0] will be reported in bit
Figure 39 on page429
(Table
204)
(Table
(Table
(Table 204 on page168
173) mask bit is set, VT_LOPS_D[1—28] will generate an interrupt.
VT_SF_ESF
181) is set to a 1,
(Table
173) mask bit is set,
[1—28]
0*
0
X
1
1
X
†
204)
) will perform all necessary functions to extract and transmit
(Table
VT_LOPS
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
[1—28]
VT_
), the RX_VTSIG block will synchronize to the incom-
X
X
X
0
0
1
VT_
177)
J2TIM[1—28] will contribute to automatic AIS gen-
J2TIM_D[1—28] = 1 will generate an interrupt.
(Table
Pass F-bit transparently.
Overwrite outgoing F bit with ESF pattern.
Overwrite outgoing F bit with SF pattern.
Overwrite outgoing F bit with ESF pattern.
Overwrite outgoing F bit with SF pattern.
Transmit DS1 AIS downstream.
177) and VT_LOPS_D[1—28]
TMXF28155/51 Super Mapper
VT_
(Table
J2TIM_D[1—28]
182). Any change in
Action
(Table
Table
(Table
169).
204).
67)
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