tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 19

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tmxf28155

Manufacturer Part Number
tmxf28155
Description
Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
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Part Number:
tmxf281553BAL3C
Manufacturer:
DSP
Quantity:
5
May 2001
3 Pin Information
Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)
3.3.4 TOAC and POAC
The transport and path overhead access channels (TOAC and POAC) allow parts of the SONET/SDH overhead to
be examined externally (receive direction) or overwritten (transmit direction) through serial data ports. Each port
has clock and data lines and synchronization signal that marks the last bit of the frame so that the rest of the over-
head bytes can be identified.
The receive TOAC and POAC channels contain all of the respective overheads bytes. The transmit channels con-
tain space for all the overhead bytes, but whether they are actually transmitted depend on how the device is pro-
grammed. Some overhead bytes can not be modified; others may be modified only through the CPU port; some
may be modified only through the overhead access channels; and some may be modified either through the CPU
port, or through the overhead access channels.
Table 6. TOAC and POAC
Agere Systems Inc.
AD1
AD3
AA5
AB6
AE2
AE3
AD4
AF3
Pin
AC3
AD2
Pin
RTOACSYNC
TTOACSYNC
RPOACDATA
RTOACDATA
TTOACDATA
RPOACCLK
RTOACCLK
TTOACCLK
TLSSYNC52
Symbol
Symbol
TLSC52
(continued)
Type
Path Overhead Access Channel (POAC)
Type
Pull down
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
Transmit Low-speed Clock. When in output (master) mode,
it is the transmit side 51.84 MHz clock output synchronous to
transmit high-speed input clock. When in input mode, it
receives a 51.84 MHz clock input synchronous to transmit
high-speed input clock
Note: TLSCLK is used as the master clock for the T1/E1
Transmit Low-speed Sync. When in output (master) mode,
it is the transmit side frame sync output synchronous to
51.84 MHz output. When in input (slave) mode, it receives the
transmit side frame sync input synchronous to 51.84 MHz
input.
Receive TOAC Clock. Receive side serial access channel
clock output for the transport overhead bytes.
Receive TOAC Data. Receive side serial access channel
data output for the transport overhead bytes.
Receive TOAC Synchronization. Receive side sync output
for TOAC channel. Active-high during the LSB of the last
byte.
Transmit TOAC Clock. Transmit side serial access channel
clock output for the transport overhead bytes.
Transmit TOAC Data. Transmit side serial access channel
data input for the transport overhead bytes.
Transmit TOAC Synchronization. Transmit side sync out-
put for TOAC channel. Active-high during the LSB of the last
byte.
Receive POAC Clock. Receive side serial access channel
clock output for the path overhead bytes.
Receive POAC Data. Receive side serial access channel
data output for the path overhead bytes.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
framer and should therefore be provided even if the
TMUX SPE and VT mappers are not used.
Description
Description
19

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