tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 510

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Table 590. Shared Rx FDL Stack Format for DDS Frames
Starting at every superframe boundary, the data link bits are stored in an internal copy of the shared Rx stack. As
the data link bits are accumulated, the data link bits from the first superframe are stored in word 0. The frame
aligner block will give an indication of loss of frame alignment, which is used by the data link block to determine if
the data link bits collected are invalid. In this case, they will not be made available to the system.
When the entire stack has been filled (three superframes), the host is notified using the Rx stack ready interrupt.
After the Rx stack ready interrupt bit is set, the host has approximately 4.5 ms to read the stack.
21.22.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack
CEPT frames are numbered 0 through 15 with the Sa bits located in time slot 0 of the odd numbered frames. The
Sa bits can only be extracted from CEPT links when the proper alignment has been established.
For basic CEPT frames, the Sa bits will be extracted given the arbitrary alignment selected by the frame aligner
block when basic frame alignment is established. For CEPT CRC-4 links, the Sa bits will be extracted based on the
alignment determined by the frame aligner block when multiframe frame alignment is established.
Optionally, the Sa bits will be extracted from CEPT CRC-4 links only after basic frame alignment is established
(RxCRCSM).
The Sa bits are stored in the stack as follows:
Table 591. Shared Rx Stack Format for CEPT Frames
It takes two multiframes to fill the Rx stack; bit 15 is received first. The frame aligner block will give an indication of
loss of frame alignment which is used by the data link block to determine if the Sa bits collected are invalid. In this
case, they will not be made available to the system.
When the entire stack has been filled, the host is notified using the Rx stack ready interrupt. After the Rx stack
ready interrupt bit is set, the host has approximately 4 ms to read the stack.
510
Word
Word
Extracts two multiframes of Sa bits from CEPT links and stores them in internal memory.
Supports loss of frame status.
Provides host access to the stack using the processor clock.
Provides interrupt for stack ready.
0
1
2
3
4
0
1
2
3
4
SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415 SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415
SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515 SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515
SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615 SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615
SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715 SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715
SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815 SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815
15
D1
D1
D1
15
—
—
14
D2
D2
D2
14
—
—
13
D3
D3
D3
13
—
—
12
D4
D4
D4
12
—
—
11
D5
D5
D5
11
—
—
10
D6
D6
D6
10
—
—
D7
D7
D7
9
—
—
9
D8
D8
D8
—
—
8
8
D9
D9
D9
—
—
7
7
D10
D10
D10
—
—
6
6
(continued)
D11
D11
D11
5
—
—
5
4
D12
D12
D12
—
—
4
3
—
—
—
—
—
3
Agere Systems Inc.
2
—
—
—
—
—
2
May 2001
1
—
—
—
—
—
1
—
—
—
—
—
0
0