tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 518

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
21 28-Channel Framer Block Functional Description
(continued)
An opening flag is always generated at the beginning of a frame (indicated by the presence of data in the transmit
FIFO and the transmitter enabled). FRM_CFLAGS[1:0]
(Table
435) determines which FRM_FCNT[0—3][4:0]
parameter to use. The FRM_FCNT[0—3][4:0] parameters define the number of idle flags that are sent between
HDLC packets. Data is transmitted per the HDLC protocol until a byte is read from the FIFO with Tx HDLC register
bits FRM_HTFUNC[1:0]
(Table
438) = 01 set. The HDLC block follows this byte with the CRC sequence and a clos-
ing flag.
The HDLC receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recog-
nized by the HDLC block). When another flag is identified, it is treated as the closing flag. As mentioned above, a
flag sequence in the user data or FCS fields is prevented by zero-bit insertion and deletion.
21.24.3 Aborts
The bit pattern of the abort sequence is 01111111, with 0 transmitted first. A frame can be aborted by writing set-
ting Tx HDLC register bits FRM_HTFUNC[1:0] = 01. This causes the last byte written to the transmit FIFO to be fol-
lowed by the abort sequence upon transmission. Once a byte is tagged by a write to Tx HDLC register bits
FRM_HTFUNC[1:0] = 01, it cannot be cleared by subsequent writes.
When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven
consecutive ones. This status results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits,
being set in the status of frame status byte which is appended to the receive data queue. The last bytes of user
data are assumed to be CRC bits and are placed in the queue in the regular HDLC mode. All subsequent
FRM_IDLE or flag bytes are ignored until a valid opening flag is received.
21.24.4 Receive IDLES
In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle.
When the HDLC block receives 15 contiguous ones, the receiver FRM_IDLE[7:0] bit, idle is set.
21.24.5 CRC
For a given frame of bits, 16 additional bits that constitute an error-detecting code are added by the transmitter. As
called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit first and are bit
stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits
by using the ITU-T standard polynomial:
16
12
5
x
+ x
+ x
+ 1
At the other end, the receiver performs the same calculation on the received bits after destuffing and compares the
results to an expected result. An error occurs if, and only if, there is a mismatch.
The transmitter can be instructed to transmit a corrupted CRC by setting the transmit bad CRC bit DXBCRC
(DCI-DCR-1-B6). As long as the DXBCRC bit is set, the CRC is corrupted for each frame transmitted by logically
flipping the least significant bit of the transmitted CRC.
The receiver calculates and verifies the CRC for an incoming frame. The result of the CRC check is reported in bit
7 of the status of frame byte, which is placed in the receive FIFO after the last data byte of the frame. The CRC is
stored in the FIFO at all times.
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Agere Systems Inc.