tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 88

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Note: In
Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Note: In
Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
88
Address
0x4000B
Address
0x4000C
change in state has taken place.
change in state has taken place.
Table
Table
15:6
Bit
Bit
15
14
13
12
11
10
85, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
86, the mask bits are set to suppress an interrupt when the corresponding event has occurred or
5
4
3
2
1
9
8
7
6
5
4
3
2
1
0
TMUX_RPSILOCM Receive Protection High-speed Loss of Input Clock Mask.
TMUX_RLRDIMONM Receive Line RDI Monitor Mask. See
TMUX_RPSLREIM Receive Protection High-speed Line REI Mask. See
TMUX_RLAISMONM Receive Line AIS Monitor Mask. See
TMUX_RPSOOFM Receive Protection High-speed Out of Frame Mask. See
TMUX_RAPSMONM Receive APS Monitor Mask. See
TMUX_RPSLOFM Receive Protection High-speed Loss of Frame Mask. See
TMUX_RAPSBABM
TMUX_RHSILOCM
TMUX_RS1MONM
TMUX_RK2MONM
TMUX_RF1MONM
TMUX_RHSOOFM
TMUX_RPSB2M
TMUX_RHSLOSM
TMUX_RHSLOFM
TMUX_RS1BABM
TMUX_RHSSDM
TMUX_RHSSFM
TMUX_RTIMSM
(continued)
Name
Name
—
—
Reserved.
Table 81
Table 81
See
Receive Protection High-speed B2 Error Mask. See
Table 81
Table 81
Reserved.
Receive S1 Babble Mask. See
Receive S1 Monitor Mask. See
tion.
tion.
Receive K2 Monitor Mask. See
Receive APS Babble Mask. See
Receive F1 Monitor Mask. See
Receive Section Trace Identifier Mismatch Mask. See
Table 82
Receive High-speed Signal Fail BER Algorithm Mask.
See
Receive High-speed Signal Degrade BER Algorithm
Mask. See
Receive High-speed Loss of Signal Mask. See
for description.
Receive High-speed Loss of Frame Mask. See
for description.
Receive High-speed Out of Frame Mask. See
description.
Receive High-speed Loss of Input Clock Mask. See
Table 82
Table 81
Table 82
for description.
for description.
for description.
for description.
for description.
for description.
Table 82
for description.
for description.
for description.
Function
Function
Table 82
Table 82
Table 82
Table 82
Table 82
Table 82
Table 82
Table 82
for description.
for description.
for description.
for description.
for description.
for description.
Table 82
for descrip-
for descrip-
Table 82
Table 82
Agere Systems Inc.
for
May 2001
Default
Default
Reset
Reset
0x000
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1