HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 992

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Pin
Name Mode Reset
PB
PB
PB
PB
PB
Legend
H:
L:
T:
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR:
Notes: *1 When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
3
5
4
7
6
,
,
1 to 5
7
1 to 5
7
1 to
5, 7
High
Low
High-impedance state
Data direction register
*2 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
*3 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*4 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*5 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
*6 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
*7 When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
*8 When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
cleared to 0.
set to 1.
register A) is 010, 100, or 101.
register A) is other than 010, 100, 101, or 000.
cleared to 0.
set to 1.
to 0.
T
T
T
T
T
Hardware
Standby
Mode
T
T
T
T
T
Software Standby
Mode
RAS
(SSOE=0)
T
(SSOE=1)
H
CS output*
(SSOE=0)
T
(SSOE=1)
H
Otherwise*
Keep
Keep
CAS output*
(SSOE=0)
T
(SSOE=1)
H
Otherwise*
Keep
Keep
Keep
4
output*
13
14
16
15
12
Bus-Released
Mode
RAS
T
CS output*
T
Otherwise*
Keep
—
CAS output*
T
Otherwise*
Keep
—
Keep
4
output*
13
14
16
Rev. 2.0, 06/04, page 963 of 980
15
12
Program Execution
Mode
RAS
RAS
CS output
CS
Otherwise
I/O port
I/O port
CAS output
UCAS, LCAS
Otherwise
I/O port
I/O port
I/O port
4
4
4
output