HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 647

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The details of the programming procedure are described below. The procedure program must be
executed in an area other than the flash memory to be programmed. Especially the part where the
SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 18.10.3, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the invalid data to be added is H'FF, the program processing period can be shorted.
Rev. 2.0, 06/04, page 618 of 980
set download destination
JSR FTDAR setting+32
Select on-chip program
to be downloaded and
Set the FPEFEQ and
FUBRA parameters
procedure program
Set SCO to 1 and
execute download
Start programming
Set FKEY to H'A5
Clear FKEY to 0
Initialization
FPFR=0?
DFPR=0?
by FTDAR
1
Yes
Yes
Initialization error processing
Download error processing
Figure 18.11 Programming Procedure
No
No
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
No
ER1 (FMPAR and FMPDR)
Disable interrupts and bus
Set parameter to ER0 and
JSR FTDAR setting+16
master operation other
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
programming is
Programming
Required data
completed?
FPFR=0?
than CPU
1
Yes
Yes
Clear FKEY and
error processing
No
programming
(i)
(j)
(k)
(l)
(m)
(n)
(o)