HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 18

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
5.3
5.4
5.5
Section 6 Bus Controller....................................................................................113
6.1
6.2
6.3
Register Descriptions ........................................................................................................ 88
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 99
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 104
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 111
5.5.1
5.5.2
5.5.3
Overview........................................................................................................................... 113
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 118
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 135
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 135
6.2.12 Address Control Register (ADRCR).................................................................... 136
Operation .......................................................................................................................... 137
6.3.1
6.3.2
6.3.3
6.3.4
System Control Register (SYSCR) ...................................................................... 88
Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 89
IRQ Status Register (ISR).................................................................................... 96
IRQ Enable Register (IER) .................................................................................. 97
IRQ Sense Control Register (ISCR) .................................................................... 98
External Interrupts ............................................................................................... 99
Internal Interrupts ................................................................................................ 100
Interrupt Vector Table ......................................................................................... 100
Interrupt Sequence ............................................................................................... 109
Features................................................................................................................ 113
Block Diagram ..................................................................................................... 115
Pin Configuration................................................................................................. 116
Register Configuration......................................................................................... 117
Access State Control Register (ASTCR) ............................................................. 119
Area Division ....................................................................................................... 137
Bus Specifications................................................................................................ 139
Memory Interfaces............................................................................................... 140
Chip Select Signals .............................................................................................. 141
Interrupt Handling Process .................................................................................. 104
Interrupt Response Time...................................................................................... 110
Contention between Interrupt and Interrupt-Disabling Instruction...................... 111
Instructions that Inhibit Interrupts ....................................................................... 112
Interrupts during EEPMOV Instruction Execution.............................................. 112
Bus Width Control Register (ABWCR)............................................................... 118
Wait Control Registers H and L (WCRH, WCRL).............................................. 119
Bus Release Control Register (BRCR) ................................................................ 123
Bus Control Register (BCR) ................................................................................ 124
Chip Select Control Register (CSCR).................................................................. 128
DRAM Control Register A (DRCRA) ................................................................. 129
DRAM Control Register B (DRCRB) ................................................................. 131
Refresh Timer Control/Status Register (RTMCSR) ............................................ 133
Rev. 2.0, 06/04, page xiii of xxiv