HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 488

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.1.4
The SCI has internal registers as listed in table 13.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, control the transmitter and receiver
sections, and specify switching between the serial communication interface and smart card
interface.
Table 13.2 SCI Registers
Channel
0
1
2
Notes: *1 Indicates the lower 20 bits of the address in advanced mode.
*2 Only 0 can be written, to clear flags.
Register Configuration
Address*
H'FFFB0
H'FFFB1
H'FFFB2
H'FFFB3
H'FFFB4
H'FFFB5
H'FFFB6
H'FFFB8
H'FFFB9
H'FFFBA
H'FFFBB
H'FFFBC
H'FFFBD
H'FFFBE
H'FFFC0
H'FFFC1
H'FFFC2
H'FFFC3
H'FFFC4
H'FFFC5
H'FFFC6
1
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Smart card mode register
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Smart card mode register
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Smart card mode register
Abbreviation
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Rev. 2.0, 06/04, page 459 of 980
R/W
R/W
R/W
R/W
R/W
R/(W)*
R
R/W
R/W
R/W
R/W
R/W
R/(W)*
R
R/W
R/W
R/W
R/W
R/W
R/(W)*
R
R/W
2
2
2
Initial Value
H'00
H'FF
H'00
H'FF
H'84
H'00
H'F2
H'00
H'FF
H'00
H'FF
H'84
H'00
H'F2
H'00
H'FF
H'00
H'FF
H'84
H'00
H'F2