HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 337

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Pin
PB
TMIO
DREQ
PB
TMO
Rev. 2.0, 06/04, page 308 of 980
3
2
/TP
/TP
2
3
/CS
/
1
11
/CS
10
/
/
5
4
Pin Functions and Selection Method
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits
CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB
function as follows.
DRAM interface
settings
OIS3/2 and OS1/0
CS4E
PB
NDER11
Pin function
Notes:
DRAM interface
settings
DRAS2
DRAS1
DRAS0
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit
CS5E in CSCR, bit NDER10 in NDERB, and bit PB
DRAM interface
settings
OIS3/2 and OS1/0
CS5E
PB
NDER10
Pin function
Note: * CS
DRAM interface
settings
DRAS2
DRAS1
DRAS0
3
2
DDR
DDR
*1 TMIO
*2 When an external request is specified as a DMAC activation source, DREQ
*3 CS
5
is output as RAS
bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB
4
is output as RAS
3
input when CCLR1 = CCLR0 = 1.
5
input
0
input
0
.
PB
PB
—
—
0
0
3
2
0
0
4
.
1
1
output
output
PB
PB
(1)
0
1
0
0
0
1
0
0
3
2
(1)
0
0
All 0
2
All 0
DDR select the pin function as follows.
(1) in table below
(1) in table below
1
1
output
output
TP
TP
1
1
1
1
DREQ
TMIO
11
10
1
1
3
1
input*
input*
output
output
0
0
CS
CS
—
—
1
—
—
1
2
1
4
5
0
0
(2)
(2)
TMIO
TMIO
1
1
3
Not all 0
Not all 0
DDR select the pin
—
—
—
—
—
—
3
2
1
1
output
1
output
input regardless of
0
0
3
DDR.
(2) in table
(2) in table
(1)
1
1
output*
output*
below
below
CS
CS
—
—
—
—
—
—
—
—
(1)
1
4
1
5
3