HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 558

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
14.3.5
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
where, N: BRR setting (0
Table 14.4 n-Values of CKS1 and CKS0 Settings
n
0
1
2
3
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
N
0
1
2
Note: Bit rates are rounded off to one decimal place.
B: Bit rate (bit/s)
n: See table 14.4
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
: Operating frequency (MHz)
B =
Clock
10.00
13440.9
6720.4
4480.3
1488
CKS1
0
1
2
2n–1
10.7136
14400.0
7200.0
4800.0
N
(N + 1)
255)
13.00
17473.1
8736.6
5824.4
CKS0
0
1
0
1
10
6
14.2848
19200.0
9600.0
6400.0
(MHz)
16.00
21505.4
10752.7
7168.5
Rev. 2.0, 06/04, page 529 of 980
18.00
24193.5
12096.8
8064.5
20.00
26881.7
13440.9
8960.6
25.00
33602.2
16801.1
11200.7

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