HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 917

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8TCSR0—Timer Control/Status Register 0
Rev. 2.0, 06/04, page 888 of 980
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Initial value
Read/Write
Bit
Compare match/input capture flag B
0
1
R/(W)*
CMFB
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
[Setting conditions]
TCNT = TCORB
The TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
7
0
Compare match flag A
0
1
R/(W)*
CMFA
[Setting condition]
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
TCNT = TCORA
6
0
Timer overflow flag
0
1
R/(W)*
OVF
[Clearing condition]
[Setting condition]
5
0
Read OVF when OVF = 1, then write 0 in OVF
TCNT overflows from H'FF to H'00
Note: *1 TRGE is bit 7 of the A/D control register (ADCR).
TRGE
A/D trigger enable (TCSR0 only)
0
1
ADTE
*
R/W
1
4
0
ADTE
Bit 4
0
1
0
1
TCSR1
Output/input capture edge select B3 and B2
ICE in
0
1
A/D converter start requests by compare match A
or an external trigger are disabled
A/D converter start requests by compare match A
or an external trigger are enabled
A/D converter start requests by an external trigger are enabled
A/D converter start requests by compare match A are enabled
OIS3
R/W
3
0
Bit 3
OIS3
0
1
0
1
Bit 1
OS1
Output select A1 and A0
Bit 2
OIS2
OIS2
0
1
R/W
H'FFF82
0
1
0
1
0
1
0
1
2
0
Bit 0
OS0
Description
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
0
1
0
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
OS1
R/W
1
0
Description
Description
OS0
R/W
0
0
8-bit timer channel 0