HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 253

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.4
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match.
Repeat mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCRH are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-
full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 7.8 indicates the register functions in repeat mode.
Table 7.8
Rev. 2.0, 06/04, page 224 of 980
Register
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
23
23
All 1s
Memory address register
Repeat Mode
MAR
Register Functions in Repeat Mode
7
7
7
ETCRH
ETCRL
IOAR
0
0
0
0
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer counter
Initial transfer count
Function
Other
Activation Initial Setting
Source
address
register
Destination
address
register
Destination or
source start
address
Source or
destination
address
Number of
transfers
Number of
transfers
Operation
Incremented or
decremented at
each transfer until
ETCRH reaches
H'0000, then restored
to initial value
Held fixed
Decremented once
per transfer until
H'0000 is reached,
then reloaded from
ETCRL
Held fixed