HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 200

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T
and two RAS output cycle (T
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
Note: * In address update mode 1, the area 2 start address is output.
Refresh request signal
and CMF bit setting signal
In address update mode 2, the address in the preceding bus cycle is retained.
RTCNT
RTCOR
Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
Address bus*
(
PB
4
/PB
/
n
(
(
5
)
)
R1
Figure 6.27 Compare Match Timing
)
, T
R2
) states. Either one or two states can be selected for the RAS
T
Rp
N
High
Area 2 start address
High level
T
R1
N
Rev. 2.0, 06/04, page 171 of 980
T
R2
H'00
RP
) state,