HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 190

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
6.5.7
In the H8/3029, provision is made for the DRAM RAS precharge time by always inserting one
RAS precharge state (T
setting the TPC bit to 1 in DRCRB. The optimum number of T
the DRAM connected and the operating frequency of the H8/3029 chip. Figure 6.19 shows the
timing when two T
Read access
Write access
When the TCP bit is set to 1, two T
Precharge State Control
Note: n = 2 to 5
(
PB
PB
Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB)
p
states are inserted.
4
4
D
D
A
/
/
/PB
/PB
p
23
15
15
) when DRAM space is accessed. This can be changed to two T
(
(
(
to A
to D
to D
5
5
)
)
)
)
0
0
0
)
p
states are also used for CAS-before-RAS refresh cycles.
T
p
High level
Row
Tr
High level
p
cycles should be set according to
Rev. 2.0, 06/04, page 161 of 980
T
Column
c1
T
c2
p
states by

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