HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 142

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1
The H8/3029 has an on-chip bus controller (BSC) that manages the external address space divided
into eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an
external device.
6.1.1
The features of the bus controller are listed below.
Manages external address space in area units
Basic bus interface
DRAM interface
Burst ROM interface
Manages the external space as eight areas (0 to 7) of 128 kbytes in 1-Mbyte modes, or 2
Mbytes in 16-Mbyte modes
Bus specifications can be set independently for each area
DRAM/burst ROM interfaces can be set
Chip select (CS
8-bit access or 16-bit access can be selected for each area
Two-state access or three-state access can be selected for each area
Program wait states can be inserted for each area
Pin wait insertion capability is provided
DRAM interface can be set for areas 2 to 5
Row address/column address multiplexed output (8/9/10 bits)
2-CAS byte access mode
Burst operation (fast page mode)
T
Choice of CAS-before-RAS refreshing or self-refreshing
Burst ROM interface can be set for area 0
Selection of two- or three-state burst access
P
Overview
Features
cycle insertion to secure RAS precharging time
0
to CS
Section 6 Bus Controller
7
) can be output for areas 0 to 7
Rev. 2.0, 06/04, page 113 of 980