HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 222
![MCU 5V 512K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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The bus right is transferred when the DMAC finishes transferring one byte or one word. A
DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred
between the read cycle and the write cycle.
There is a priority order among the DMAC channels. For details see section 7.4.9, Multiple-
Channel Operation.
DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh
cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section
6.5, DRAM Interface.
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it
keeps the bus until the BREQ signal goes high. While the bus is released to an external bus
master, the H8/3029 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and
LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK
pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock ( ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the
bus-release cycle.
Figure 6.48 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
BREQ signal goes low until the bus is released.
Rev. 2.0, 06/04, page 193 of 980
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