HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 367

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
0
1
Notes: *1 After a reset, the output conforms to the TOLR setting until the first compare match.
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
0
1
Notes: *1 After a reset, the output conforms to the TOLR setting until the first compare match.
Rev. 2.0, 06/04, page 338 of 980
*2 Channel 2 output cannot be toggled by compare match. When this setting is made, 1
*2 Channel 2 output cannot be toggled by compare match. When this setting is made, 1
Bit 1
IOA1
0
1
0
1
Bit 5
IOB1
0
1
0
1
output is selected automatically.
output is selected automatically.
Bit 4
IOB0
0
1
0
1
0
1
0
1
Bit 0
IOA0
0
1
0
1
0
1
0
1
GRB is an output
GRB is an input
Function
GRA is an output
compare register
GRA is an input
compare register
Function
compare register
compare register
No output at compare match
0 output at GRB compare match*
1 output at GRB compare match*
Output toggles at GRB compare match
(1 output in channel 2)*
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
No output at compare match
0 output at GRA compare match*
1 output at GRA compare match*
Output toggles at GRA compare match
(1 output in channel 2)*
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
1
1
*
*
2
2
(Initial value)
(Initial value)
1
1
1
1