HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 524

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
13.3.3
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor stars by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming
data until they again receive data with the multiprocessor bit set to 1. Multiple processors can
send and receive data in this way.
Figure 13.9 shows an example of communication among different processors using a
multiprocessor format.
RDRF
FER
1
Multiprocessor Communication
Start
bit
0
D0
D1
Figure 13.8 Example of SCI Receive Operation
1 frame
(8-Bit Data with Parity and One Stop Bit)
Data
D7
Parity
bit
RXI request
0/1
Stop
bit
1
Start
bit
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
0
D0
D1
Rev. 2.0, 06/04, page 495 of 980
Data
D7
Stop
bit
Parity
bit
0/1
Framing error,
ERI request
Stop
bit
Idle (mark) state
1
1