HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 906

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TISRA—Timer Interrupt Status Register A
Note: * Only 0 can be written, to clear the flag.
Input capture/compare match interrupt enable A2
0
1
Input capture/compare match interrupt enable A1
IMIA2 interrupt requested by IMFA2 flag is disabled
IMIA2 interrupt requested by IMFA2 flag is enabled
0
1
Input capture/compare match interrupt enable A0
0
1
IMIA1 interrupt requested by IMFA1 flag is disabled
IMIA1 interrupt requested by IMFA1 flag is enabled
Read/Write:
Bit:
Initial value:
Input capture/compare match flag A2
IMIA0 interrupt requested by IMFA0 flag is disabled
IMIA0 interrupt requested by IMFA0 flag is enabled
0
1
Input capture/compare match flag A1
[Clearing conditions]
Read IMFA2 when IMFA2=1, then write 0 in IMFA2
DMAC activated by IMIA2 interrupt.
[Setting conditions]
TCNT2=GRA2 when GRA2 functions as an output compare register.
TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register.
0
1
Input capture/compare match flag A0
0
1
[Clearing conditions]
Read IMFA1 when IMFA1=1, then write 0 in IMFA1
DMAC activated by IMIA1 interrupt.
[Setting conditions]
TCNT1=GRA1 when GRA1 functions as an output compare register.
TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register.
—
—
7
1
[Clearing conditions]
Read IMFA0 when IMFA0=1, then write 0 in IMFA0
DMAC activated by IMIA0 interrupt.
[Setting conditions]
TCNT0=GRA0 when GRA0 functions as an output compare register.
TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register.
IMIEA2
R/W
6
0
IMIEA1
R/W
5
0
IMIEA0
R/W
4
0
H'FFF64
—
—
3
1
IMFA2
R/(W)*
(Initial value)
2
0
(Initial value)
IMFA1
R/(W)*
Rev. 2.0, 06/04, page 877 of 980
1
0
(Initial value)
16-bit timer (all channels)
R/(W)*
IMFA0
(Initial value)
0
0
(Initial value)
(Initial value)