HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 19

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.5
6.6
6.7
6.8
6.9
6.10 Bus Arbiter........................................................................................................................ 192
6.11 Register and Pin Input Timing .......................................................................................... 195
Section 7 DMA Controller ................................................................................197
7.1
Rev. 2.0, 06/04, page xiv of xxiv
6.3.5
Basic Bus Interface ........................................................................................................... 144
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
DRAM Interface ............................................................................................................... 157
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 165
6.5.11 Refresh Control.................................................................................................... 170
6.5.12 Examples of Use .................................................................................................. 174
6.5.13 Usage Notes ......................................................................................................... 178
Interval Timer ................................................................................................................... 181
6.6.1
Interrupt Sources............................................................................................................... 186
Burst ROM Interface......................................................................................................... 186
6.8.1
6.8.2
6.8.3
Idle Cycle .......................................................................................................................... 188
6.9.1
6.9.2
6.10.1 Operation ............................................................................................................. 192
6.11.1 Register Write Timing ......................................................................................... 195
6.11.2 BREQ Pin Input Timing ...................................................................................... 196
Overview........................................................................................................................... 197
7.1.1
7.1.2
7.1.3
Address Output Method....................................................................................... 142
Overview.............................................................................................................. 144
Data Size and Data Alignment............................................................................. 144
Valid Strobes....................................................................................................... 145
Memory Areas ..................................................................................................... 146
Basic Bus Control Signal Timing ........................................................................ 148
Wait Control ........................................................................................................ 155
Overview.............................................................................................................. 157
DRAM Space and RAS Output Pin Settings ....................................................... 157
Address Multiplexing........................................................................................... 158
Data Bus............................................................................................................... 159
Pins Used for DRAM Interface............................................................................ 159
Basic Timing........................................................................................................ 160
Precharge State Control ....................................................................................... 161
Wait Control ........................................................................................................ 162
Byte Access Control and CAS Output Pin........................................................... 163
Operation ............................................................................................................. 181
Overview.............................................................................................................. 186
Basic Timing........................................................................................................ 186
Wait Control ........................................................................................................ 187
Operation ............................................................................................................. 188
Pin States in Idle Cycle ........................................................................................ 191
Features................................................................................................................ 197
Block Diagram ..................................................................................................... 198
Functional Overview............................................................................................ 199