HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 724

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
19.5.1
Table 19.4 summarizes the frequency division register.
Table 19.4 Frequency Division Register
Address*
H'EE01B
Note:
19.5.2
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1
0
0
1
1
Bit
Initial value
Read/Write
* Lower 20 bits of the address in advanced mode.
Bit 0
DIV0
0
1
0
1
Register Configuration
Division Control Register (DIVCR)
Name
Division control register
Frequency Division Ratio
1/1
1/2
1/4
1/8
7
1
6
1
Reserved bits
5
1
Abbreviation
DIVCR
4
1
3
1
R/W
R/W
Rev. 2.0, 06/04, page 695 of 980
2
1
Divide bits 1 and 0
These bits select the
frequency division ratio
DIV1
R/W
Initial Value
H'FC
1
0
(Initial value)
DIV0
R/W
0
0

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