HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 523

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In receiving, the SCI operates as follows:
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
Table 13.11 Receive Error Conditions
Receive Error Abbreviation Condition
Overrun error ORER
Framing error FER
Parity error
Rev. 2.0, 06/04, page 494 of 980
The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
synchronizes internally and starts receiving.
Receive data is stored in RSR in order from LSB to MSB.
The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks:
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If
one of the checks fails (receive error*), the SCI operates as shown in table 13.11.
When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Parity check: The number of 1s in the receive data must match the even or odd parity
setting of in the O/E bit in SMR.
Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
checked.
Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
from RSR into RDR.
is not set to 1. Be sure to clear the error flags to 0.
PER
Receiving of next data ends while
RDRF flag is still set to 1 in SSR
Stop bit is 0
Parity of received data differs from
even/odd parity setting in SMR
Data Transfer
Receive data is not transferred
from RSR to RDR
Receive data is transferred from
RSR to RDR
Receive data is transferred from
RSR to RDR