HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 630

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Flash user branch address setting parameter (FUBRA: general register ER1 of CPU)
This parameter sets the user branch destination address. The user program which has been set can
be executed in specified processing units when programming and erasing.
Bits 31 to 0—User Branch Destination Address (UA31 to UA0): Not available in the H8/3029,
address 0 (H'00000000) must be set.
The user branch destination must be the area other than the RAM area in which on-chip program
has been transferred or the external bus space.
Note that the CPU must not branch to an area without the execution code and get out of control.
The on-chip program download area and stack area must not be overwritten. If CPU runaway
occurs or the download area or stack area is overwritten, the value of flash memory cannot be
guaranteed.
The download of on-chip program, initialization, initiation of the programming/erasing program
must not be executed in the processing of the user branch destination. Programming or erasing
cannot be guaranteed when returning from the user branch destination. The program data which
has already been prepared must not be programmed.
Moreover, the programming/erasing interface register must not be programmed or RAM
emulation mode must not be entered in the processing of the user branch destination.
After the processing of the user branch is ended, the programming/erasing program must be
returned by using the RTS instruction.
(c) Flash pass/fail parameter (FPFR: general register R0L of CPU)
An explanation of FPFR as the return value indicating the initialization result is provided here.
Bits 7 to 3—Unused: Return 0.
Bit :
Bit :
Bit :
Bit :
Bit :
UA31
UA23
UA15
UA7
31
23
15
7
7
0
UA30
UA22
UA14
UA6
30
22
14
6
6
0
UA29
UA21
UA13
UA5
29
21
13
5
5
0
UA28
UA20
UA12
UA4
28
20
12
4
4
0
UA27
UA19
UA11
UA3
27
19
11
3
3
0
Rev. 2.0, 06/04, page 601 of 980
UA26
UA18
UA10
UA2
BR
26
18
10
2
2
UA25
UA17
UA9
UA1
FQ
25
17
9
1
1
UA24
UA16
UA8
UA0
24
16
SF
8
0
0