HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 94

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.4
Ports 1, 2, 5, and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A
used for address output.)
3.4.5
Ports 1, 2, 5, and part of port A can function as address pins A
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A
on-chip flash memory support on-board programming which enables programming of the flash
memory. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one
area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.
Products with on-chip flash memory support on-board programming which enables programming
of the flash memory.
23
Mode 4
Mode 5
Mode 7
to A
21
are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A
23
to A
20
output, write 0 in bits 7 to 4 of BRCR. Products with
23
to A
23
to A
0
, permitting access to a
Rev. 2.0, 06/04, page 65 of 980
0
, permitting access to a
20
is always