HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 305
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HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8.7.2
Table 8.10 summarizes the registers of port 6.
Table 8.10 Port 6 Registers
Address*
H'EE005
H'FFFD5
Note:
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bit 7 is reserved. It is fixed at 1, and cannot be modified.
Modes 1 to 5 (Expanded Modes): P6
the clock output pin ( ) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input
port if this bit is set to 1.
P6
settings of bits P6
P6
ports. For the method of selecting the pin functions, see table 8.11.
When P6
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
Mode 7 (Single-Chip Mode): P6
P6
MSTCRH is cleared to 0, and an input port if this bit is set to 1 (initial value). A pin in port 6
becomes an output port if the corresponding bit of P6
port if this pin is cleared to 0.
Rev. 2.0, 06/04, page 276 of 980
Bit
Initial value
Read/Write
6
2
0
to P6
to P6
function as generic input/output ports. P6
* Lower 20 bits of the address in advanced mode.
3
0
2
Register Descriptions
function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output
to P6
Reserved bit
0
Name
Port 6 data direction register
Port 6 data register
function as input/output ports, the pin becomes an output port if the
6
DDR to P6
—
—
7
1
P6 DDR
3
DDR.
6
W
6
0
7
functions as the clock output pin ( ) or an input port. P6
P6 DDR
7
functions as the clock output pin ( ) or an input port. P6
5
W
5
0
7
is the clock output pin ( ) if the PSTOP bit in
P6 DDR
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
P6DDR
P6DR
Abbreviation
4
W
4
0
6
DDR to P6
P6 DDR
3
W
3
0
0
DDR is set to 1, and an input
P6 DDR
R/W
W
R/W
2
W
2
0
P6 DDR
Initial Value
H'80
H'80
1
W
1
0
P6 DDR
0
W
0
0
6
to
7
is
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