HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 645

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

damage or destroy flash memory. If reset is executed accidentally, reset must be released after the
reset input period, which is longer than normal 100 s.
For information on the programming procedure refer to “Programming Procedure in User
Program Mode”, and for information on the erasing procedure refer to “Erasing Procedure in User
Program Mode”, below.
For the overview of a processing that repeats erasing and programming by downloading the
programming program and the erasing program in separate on-chip ROM areas using FTDAR, see
“Erasing and Programming Procedure in User Program Mode” which appears later in this section.
On-chip RAM Address Map when Programming/Erasing is Executed: Parts of the procedure
program that are made by the user, like download request, programming/erasing procedure, and
judgement of the result, must be executed in the on-chip RAM. The on-chip program that is to be
downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so
that these parts do not overlap.
Figure 18.10 shows the program area to be downloaded.
Rev. 2.0, 06/04, page 616 of 980
program data is prepared
transferred to the on-chip
Programming/erasing
Programming/erasing
When programming,
Programming/erasing
procedure program is
RAM and executed
FWE=1 ?
start
end
Yes
Figure 18.9 Programming/Erasing Overview Flow
No
1. RAM emulation mode must be canceled
2. When the program data is made by means
3. Inputting the FWE pin to high level sets the
4. Programming/erasing is executed only in
5. After programming/erasing is finished, the FWE
in advance. Download cannot be executed
in emulation mode.
of emulation, use the FTDAR register to change
the download destination. Note that the download
area and the emulation area will overlap if FTDAR
is in its initial status (H'00) or set to H'01.
FWE bit to 1.
the on-chip RAM. However, if program data
is in a consecutive area and can be accessed
by the MOV.B instruction of the CPU like
SRAM/ROM, the program data can be in an
external space.
pin must be input to low and protected.